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參數(shù)資料
| 型號(hào)： | PC8265A |
| 英文描述： | PC8265A [Updated 9/03. 59 Pages] |
| 中文描述： | PC8265A [更新9 / 03。 59頁] |
| 文件頁數(shù)： | 3/59頁 |
| 文件大小： | 455K |
| 代理商： | PC8265A |
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3
PC8265A PowerQUICC II
5336A–HIREL–08/03
High-performance (6.6 - 7.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz
without inlining and 1.90 Dhrystones MIPS/MHz with inlining)
Supports bus snooping for data cache coherency
Floating-point unit (FPU)
Separate power supply for internal logic and for I/O
Separate PLLs for G2 core and for the CPM
G2 core and CPM can run at different frequencies for power/performance
optimization
Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1,
6:1 ratios
Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1
ratios
64-bit data and 32-bit address 60x bus
Bus supports multiple master designs
Supports single- and four-beat burst transfers
64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
Single-master bus, supports external slaves
Eight-beat burst transfers
32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
Programmable host bridge and agent
32-bit data bus, 66 MHz, 3.3V
Synchronous and asynchronous 60x and PCI clock modes
All internal address space available to external PCI host
DMA for memory block transfers
PCI-to-60x address remapping
System interface unit (SIU)
Clock synthesizer
Reset controller
Real-time clock (RTC) register
Periodic interrupt timer
Hardware bus monitor and software watchdog timer
IEEE 1149.1 JTAG test access port
Twelve-bank memory controller
Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other
user-definable peripherals
Byte write enables and selectable parity generation
32-bit address decoder with programmable bank size
Three user programmable machines, general-purpose chip-select machine, and
page-mode pipeline SDRAM machine
Byte selects of 64 bus width (60x) and byte selects for 32 bus width (local)
Dedicated interface logic for SDRAM
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