參數(shù)資料
型號(hào)： PC8265A
英文描述： PC8265A [Updated 9/03. 59 Pages]
中文描述： PC8265A [更新9 / 03。 59頁(yè)]
文件頁(yè)數(shù)： 48/59頁(yè)
文件大?。?/td> 455K
代理商： PC8265A
48
PC8265A PowerQUICC II
5336A–HIREL–08/03
Notes:
1. Because of speed dependencies, not all of the possible configurations in Table 15 are applicable.
2. The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU is equal
to or greater than150 MHz and the CPM ranges between 66 – 233 MHz.
3. Input clock frequency is given only for the purpose of reference. MODCK_H–MODCK_L should be set so that the resulting
configuration does not exceed the frequency rating of the user’s part.
Example. If a part is rated at 266 MHz CPU, 200 MHz CPM, and 66 MHz bus, any of the following are possible (note
that the three input clock frequencies are only three of many possible input clock frequencies):
1.
66 MHz input clock and MODCK_H–MODCK_L[0111–101] (with a core multiplication factor of 4 and a CPM
multiplication factor of 3). The resulting configuration equals the part’s maximum possible frequencies of 266
MHz CPU, 200 MHz CPM, and 66 MHz bus.
2.
50 MHz input clock and MODCK_H–MODCK_L[0111–101] to achieve a configuration of 200 MHz CPU, 150
MHz CPM, and 50 MHz bus.
3.
40 MHz input clock and MODCK_H–MODCK_L[0010–011] to achieve a configuration of 200 MHz CPU, 160
MHz CPM, and 40 MHz bus.
Note that with each example, any one of several values for MODCK_H–MODCK_L could possibly be used as long as
the resulting configuration does not exceed the part’s rating.
0110_011
66
2.5
166
2
133
0110_100
66
2.5
166
2.5
166
0110_101
66
2.5
166
3
200
0110_110
66
2.5
166
3.5
233
0110_111
66
2.5
166
4
266
0111_000
66
2.5
166
4.5
300
0111_001
66
3
200
2
133
0111_010
66
3
200
2.5
166
0111_011
66
3
200
3
200
0111_100
66
3
200
3.5
233
0111_101
66
3
200
4
266
0111_110
66
3
200
4.5
300
0111_111
66
3.5
233
2
133
1000_000
66
3.5
233
2.5
166
1000_001
66
3.5
233
3
200
1000_010
66
3.5
233
3.5
233
1000_011
66
3.5
233
4
266
1000_100
66
3.5
233
4.5
300
Table 15.
Clock Configuration Modes
(1)
(Continued)
MODCK_H–MODCK[1–3]
Input Clock
Frequency
(2)(3)
(MHz)
CPM
Multiplication
Factor
(2)
CPM
Frequency
(2)
(MHz)
Core
Multiplication
Factor
(2)
Core
Frequency
(2)
(MHz)
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