參數(shù)資料
型號： PC8240
廠商： Atmel Corp.
英文描述： Integrated Processor Family
中文描述： 綜合處理器系列
文件頁數(shù)： 37/42頁
文件大?。?/td> 421K
代理商： PC8240
37
PC8240
2149A–HIREL–05/02
The SDRAM_SYNC_OUT signal is intended to be routed halfway out to the SDRAM
devices and then returned to the SDRAM_SYNC_IN input of the PC8240. The trace
length may be used to skew or adjust the timing window as needed. See Motorola appli-
cation note AN1794/D for more information on this topic.
Pull-up/Pull-down Resistor
Requirements
The data bus input receivers are normally turned off when no read operation is in
progress; therefore, they do not require pull-up resistors on the bus. The data bus sig-
nals are: DH[0
–
31], DL[0 – 31], and PAR[0 – 7].
If the 32-bit data bus mode is selected, the input receivers of the unused data and parity
bits (DL[0 – 31], and PAR[4 – 7]) will be disabled, and their outputs will drive logic zeros
when they would otherwise normally be driven. For this mode, these pins do not require
pull-up resistors, and should be left unconnected by the system to minimize possible
output switching.
The TEST[0 – 1] pins require pull-up resistors of 120
or less connected to OVdd.
It is recommended that TEST2 have weak pull-up resistor (2
k
– 10 k
) connected to
GVdd.
It is recommended that the following signals be pulled up to OVdd with weak pull-up
resistors (2 k
– 10 k
): SDA, SCL, SMI, SRESET, TBEN, CHKSTOP_IN, TEST3, and
TEST4.
It is recommended that the following PCI control signals be pulled up to LVdd with weak
pull-up resistors (2 k
– 10 k
): DEVSEL, FRAME, IRDY, LOCK, PERR, SERR, STOP,
and TRDY. The resistor values may need to be adjusted stronger to reduce induced
noise on specific board designs.
The following pins have internal pull-up resistors enabled at all times: REQ[0 – 3],
REQ4/DA4, TCK, TDI, TMS, and TRST. See Table 1, “PC8240 Pinout Listing,” on
page 3 for more information.
The following pins have internal pull-up resistors enabled only while device is in the
reset state: GNT4/DA5, DL0, FOE, RCS0, SDRAS, SDCAS, CKE, AS, MCP, MAA[0 –
2], PMAA[0 – 2]. See Table 1, “PC8240 Pinout Listing,” on page 3 for more information.
The following pins are reset configuration pins: GNT4/DA5, DL0, FOE, RCS0, CKE, AS,
MCP, QACK/DA0, MAA[0 – 2], PMAA[0 – 2], and PLL_CFG[0 – 4]/DA[10 – 6]. These
pins are sampled during reset to configure the device.
Reset configuration pins should be tied to GND via 1 k
pull-down resistors to ensure a
logic zero level is read into the configuration bits during reset if the default logic one
level is not desired.
Any other unused active low input pins should be tied to a logic one level via weak pull-
up resistors (2
k
– 10 k
) to the appropriate power supply listed in Table 3 on page 8.
Unused active high input pins should be tied to GND via weak pull-down resistors
(2
k
– 10 k
).
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