參數資料
型號： PC8240
廠商： Atmel Corp.
英文描述： Integrated Processor Family
中文描述： 綜合處理器系列
文件頁數： 34/42頁
文件大?。?/td> 421K
代理商： PC8240
34
PC8240
2149A–HIREL–05/02
PLL Configuration
The PC8240’s internal PLLs are configured by the PLL_CFG[0–4] signals. For a given
PCI_SYNC_IN (PCI bus) frequency, the PLL configuration signals set both the Periph-
eral Logic/Memory Bus PLL (VCO) frequency of operation for the PCI-to-Memory
frequency multiplying and the 603e CPU PLL (VCO) frequency of operation for Memory-
to-CPU frequency multiplying. The PLL configuration for the PC8240 is shown in Table
19.
Notes:
1. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0 – 4] settings must be chosen such that the resulting peripheral
logic/ memory bus frequency, CPU (core) frequency, and PLL (VCO) frequencies do not exceed their respective maximum
or minimum operating frequencies shown in Table. Bold font numerical pairs indicate input range limit and limiting
parameter.
2. The processor HID1 values only represent the multiplier of the processor’s PLL (Memory to Processor Multiplier), thus mul-
tiple PC8240 PLL_CFG[0 – 4] values may have the same processor HID1 value. This implies that system software cannot
read the HID1 register and associate it with a unique PLL_CFG[0 – 4] value.
3. PLL_CFG[0 – 4] settings not listed (00110, 01001, 01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and 11011)
are reserved.
4. In PLL Bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is dis-
abled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for factory use only. The AC timing
specifications given in this document do not apply in PLL Bypass mode.
Table 19.
PC8240 Microprocessor PLL Configuration
Ref
PLL_ CFG
[0 – 4]
(1)(3)
CPU HID1
[0 – 4]
(2)
200 MHz Part
(9)
Ratios
(4)(5)
PCI Clock Input
(PCI_ SYNC_IN)
Range
(MHz)
Periph Logic/
Mem Bus Clock
Range (MHz)
CPU Clock
Range (MHz)
PCI to Mem
(Mem VCO)
Multiplier
Mem to CPU
(CPU VCO)
Multiplier
0
00000
00110
25 –
26
75 – 80
188 –
200
3
(6)
2.5
(5)
1
00001
TBD
NOT USABLE
3
(6)
3
(6)
2
00010
TBD
50 – 56
(6)
50 – 56
100 – 112
1
(4)
2
(8)
3
00011
TBD
Bypass
Bypass
2
(8)
4
00100
00101
25 – 28
(6)
50 – 56
100 – 113
2
(8)
2
(8)
5
00101
TBD
Bypass
Bypass
2.5
(5)
7
00111
TBD
Bypass
Bypass
3
(6)
8
01000
11000
33
(7)
– 56
(6)
33 – 56
100 – 168
1
(4)
3
(6)
A
01010
TBD
NOT USABLE
2
(4)
4.5
(9)
C
01100
00110
25 –
40
50 – 80
125 –
200
2
(4)
2.5
(5)
E
01110
11000
25 –
33
50 – 66
150 –
200
2
(4)
3
(6)
10
10000
00100
25 –
33
75 – 100
150 –
200
3
(6)
2
(4)
12
10010
00100
33
(8)
–
66
50 – 100
100 –
200
1.5
(3)
2
(4)
14
10100
11110
25 –
28
50 – 56
175 –
200
2
(4)
3.5
(7)
16
10110
11010
25
50
200
2
(4)
4
(8)
18
11000
11000
25 –
26
62 – 65
186 –
200
2.5
(5)
3
(6)
1A
11010
11010
50
50
200
1
(2)
4
(8)
1C
11100
11000
3 –
44
50 – 66
150 –
200
1.5
(3)
3
(6)
1D
11101
00110
33
(8)
–
53
50 – 80
125 –
200
1.5
(3)
2.5
(5)
1E
11110
TBD
Off
Off
1F
11111
TBD
Off
Off
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