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參數(shù)資料
| 型號： | PC8240 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 35/42頁 |
| 文件大?。?/td> | 421K |
| 代理商： | PC8240 |
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35
PC8240
2149A–HIREL–05/02
5. In Clock Off mode, no clocking occurs inside the PC8240 regardless of the PCI_SYNC_IN input.
6. Limited due to maximum memory VCO = 225 MHz.
7. Limited due to minimum CPU VCO = 200 MHz.
8. Limited due to minimum memory VCO = 100 MHz.
9. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity.
System Design
Information
This section provides electrical and thermal design recommendations for successful
application of the PC8240.
PLL Power Supply Filtering
The AVdd, AVdd2, and LAVdd power signals are provided on the PC8240 to provide
power to the peripheral logic/memory bus PLL, the 603e processor PLL, and the
SDRAM clock delay-locked loop (DLL), respectively. To ensure stability of the internal
clocks, the power supplied to the AVdd, AVdd2, and LAVdd input signals should be fil-
tered of any noise in the 500 kHz to 10 MHz resonant frequency range of the PLLs. A
separate circuit similar to the one shown in Figure 26 using surface mount capacitors
with minimum effective series inductance (ESL) is recommended for each of the AVdd,
AVdd2, and LAVdd power signal pins. Consistent with the recommendations of Dr.
Howard Johnson in
High Speed Digital Design: A Handbook of Black Magic
(Prentice
Hall, 1993), multiple small capacitors of equal value are recommended over using multi-
ple values.
The circuits should be placed as close as possible to the respective input signal pins to
minimize noise coupled from nearby circuits. Routing directly as possible from the
capacitors to the input signal pins with minimal inductance of vias is important but pro-
portionately less critical for the LAVdd pin.
Figure 26.
PLL Power Supply Filter Circuit
Power Supply Voltage
Sequencing
The notes in Table 3 on page 8 contain cautions illustrated in Figure 2 on page 9 about
the sequencing of the external bus voltages and internal voltages of the PC8240. These
cautions are necessary for the long term reliability of the part. If they are violated, the
electrostatic discharge (ESD) protection diodes will be forward biased and excessive
current can flow through these diodes. Figure 2 shows a typical ramping voltage
sequence where the DC power sources (voltage regulators and/or power supplies) are
connected as shown in Figure 27. The voltage regulator delay shown in Figure 2 can be
zero if the various DC voltage levels are all applied to the target board at the same time.
The ramping voltage sequence shows a scenario in which the Vdd/AVdd/AVdd2/LAVdd
power plane is not loaded as much as the OVdd/GVdd power plane and thus
Vdd/AVdd/AVdd2/LAVdd ramps at a faster rate than OVdd/GVdd.
If the system power supply design does not control the voltage sequencing, the circuit of
Figure 27 can be added to meet these requirements. The MUR420 diodes of Figure 27
control the maximum potential difference between the 3.3 bus and internal voltages on
power-up and the 1N5820 Schottky diodes regulate the maximum potential difference
on power-down.
Vdd
AVdd, AVdd2, or LAVdd
2.2 μF
2.2 μF
GND
Low ESL surface mount capacitors
10 k
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