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參數(shù)資料
| 型號： | PC8240 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 27/42頁 |
| 文件大小： | 421K |
| 代理商： | PC8240 |
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27
PC8240
2149A–HIREL–05/02
4. Specified at a nominal 50 pF load.
5. D
FDR
is the decimal divider number indexed by FDR[5:0] value. Refer to the
two-wire interface
Interface chapter’s Serial
Bit Clock Frequency Divider Selections table. FDR[x] refers to the Frequency Divider Register I2CFDR bit x. N is equal to a
variable number that would make the result of the divide (Data Hold Time value) equal to a number less than 16. M is equal
to a variable number that would make the result of the divide (Data Hold Time value) equal to a number less than 9.
Figure 15.
Two-wire Interface Timing Diagram I
Figure 16.
Two-wire Interface Timing Diagram II
Figure 17.
Two-wire Interface Timing Diagram III
SCL
SDA
VM
VM
6
2
1
4
SCL
SDA
VM
VL
VH
9
8
3
5
INPUT DATA VALID
DFFSR FILTER CLK (1)
SDA
7
Note 1: DFFSR Filter Clock is the SDRAM_CLK clock times DFFSR value.
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