參數(shù)資料
型號(hào)： PC8240
廠商： Atmel Corp.
英文描述： Integrated Processor Family
中文描述： 綜合處理器系列
文件頁(yè)數(shù)： 20/42頁(yè)
文件大?。?/td> 421K
代理商： PC8240
20
PC8240
2149A–HIREL–05/02
Figure 9.
DLL Locking Range Loop Delay vs. Frequency of Operation
Input AC Timing
Specifications
Table 10 provides the input AC timing specifications. See Figure 10 on page 21 and Fig-
ure 11 on page 21.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V
± 5%
and LVdd = 3.3V ± 5%
Notes:
1. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0V) of the signal in
question to the V
M
= 1.4V of the rising edge of the memory bus clock, SDRAM_SYNC_IN. SDRAM_SYNC_IN is the same
as PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on
every rising and falling edge of PCI_SYNC_IN). See Figure 10 on page 21.
Tloop Propagation Delay Time in Nanoseconds
DLL will lock
DLL not guaranteed to lock
N = 1
DLL_EXTEND = 0
N = 2
DLL_EXTEND = 1
N = 2
DLL_EXTEND = 0
N = 1
DLL_EXTEND = 1
0 ns
5 ns
10 ns
15 ns
100 MHz
10 ns
50 MHz
20 ns
33 MHz
30 ns
25 MHz
40 ns
T
Table 10.
Input AC Timing Specifications
Num
Characteristics
Min
Max
Unit
Notes
10a
PCI Input Signals Valid to PCI_SYNC_IN (Input Setup)
2.0
–
ns
(2)(3)
10b1
Memory Control and Data Input Signals in Flow Through Mode Valid to
SDRAM_SYNC_IN (Input Setup)
4.0
–
ns
(1)(3)
10b2
Memory Control and Data Input Signals in Registered Mode Valid to
SDRAM_SYNC_IN (Input Setup)
TBD
–
ns
(1)(3)
10c
Epic, Misc. Debug Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
TBD
–
ns
(1)(3)
10d
Two-wire Interface
Input Signals Valid to SDRAM_SYNC_IN (Input Setup)
TBD
–
ns
(1)(3)
10e
Mode select Inputs Valid to HRST_CPU/HRST_CTRL (Input Setup)
9*t
CLK
–
ns
(1)(3)(5)
11a
PCI_SYNC_IN (SDRAM_SYNC_IN) to Inputs Invalid (Input Hold)
1.0
–
ns
(1)(2)(3)
11b
HRST_CPU/HRST_CTRL to Mode select Inputs Invalid (Input Hold)
TBD
–
ns
(1)(3)(5)
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