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參數(shù)資料
| 型號： | PC8240 |
| 廠商： | Atmel Corp. |
| 英文描述： | Integrated Processor Family |
| 中文描述： | 綜合處理器系列 |
| 文件頁數(shù)： | 24/42頁 |
| 文件大?。?/td> | 421K |
| 代理商： | PC8240 |
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24
PC8240
2149A–HIREL–05/02
Figure 14.
PCI_HOLD_DEL Affect on Output Valid and Hold Time
Two-wire Interface AC Timing
Specifications
Table 13 provides the two-wire interface input AC timing specifications for the PC8240.
At recommended operating conditions (see Table 3 on page 8) with GVdd = 3.3V
± 5%
and LVdd = 3.3V ± 5%
PCI_SYNC_IN
PCI INPUTS/OUTPUTS
33 MHz PCI
12a, 8 ns for 33 MHz PCI
PCI_HOLD_DEL = 100
12a, 6 ns for 66 MHz PCI
PCI_HOLD_DEL = 000
13a, 2 ns for 33 MHz PCI
PCI_HOLD_DEL = 100
13a, 1 ns for 66 MHz PCI
PCI_HOLD_DEL = 000
OUTPUT VALID
OUTPUT HOLD
Diagram Not to Scale
As PCI_HOLD_DEL
values decrease
As PCI_HOLD_DEL
values increase
PCI INPUTS
and OUTPUTS
PCI INPUTS/OUTPUTS
66 MHz PCI
0Vdd 2
0Vdd 2
Table 13.
Two-wire Interface Input AC Timing Specifications
Num
Characteristics
Min
Max
Unit
Notes
1
Start condition hold time
4.0
–
CLKs
(1)(2)
2
Clock low period
(The time before the PC8240 will drive SCL
low as a transmitting slave after detecting
SCL low as driven by an external master.)
8.0 + (16 x 2
FDR[4:2]
) x (5 -
4({FDR[5],FDR[1]} == b’10) -
3({FDR[5],FDR[1]} == b’11) -
2({FDR[5],FDR[1]} == b’00) -
1({FDR[5],FDR[1]} == b’01))
–
CLKs
(1)(2)(4)(5)
3
SCL/SDA rise time (from 0.5V to 2.4V)
–
1
mS
4
Data hold time
0
–
ns
(2)
5
SCL/SDA fall time (from 2.4V to 0.5V)
–
1
mS
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