參數(shù)資料
型號(hào)： OX9162
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Parallel Port/Local Bus and PCI interface
中文描述： 綜合并口/本地總線和PCI接口
文件頁(yè)數(shù)： 32/41頁(yè)
文件大?。?/td> 347K
代理商： OX9162
10 AC E
LECTRICAL
C
HARACTERISTICS
Data Sheet Revision 1.1 PRELIMINARY
Page 32
OX9162
OXFORD SEMICONDUCTOR LTD.
10.1 PCI Bus
The timings for PCI pins comply with PCI Specification for the 5.0 Volt signalling environment.
10.2 Local Bus
By default, the Local bus control signals change state in the cycle immediately following the reference cycle, with offsets to
provide setup and hold times for common peripherals in Intel mode. The tables below show these default values; however each
of these can be increased or decreased by an number of PCI clock cycles by adjusting the parameters in registers LT1 and LT2.
Symbol
Parameter
t
ref
IRDY# falling to reference LBCLK
t
za
Reference LBCLK to Address Valid
t
ard
Address Valid to LBRD# falling
t
zrcs1
Reference LBCLK to LBCS# falling
t
zrcs2
Reference LBCLK to LBCS# rising
t
csrd
LBCS# falling to LBRD# falling
t
rdcs
LBRD# rising to LBCS# rising
t
zrd1
Reference LBCLK to LBRD# falling
t
zrd2
Reference LBCLK to LBRD# rising
t
drd
Data bus floating to LBRD# falling
t
zd1
Reference LBCLK to data bus floating at the start of the read
transaction
t
zd2
Reference LBCLK to data bus driven by OX9162 at the end of the read
transaction
t
sd
Data bus valid to LBRD# rising
t
hd
Data bus valid after LBRD# rising
Min
Nominally 2 PCI clock cycles
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TBD
TBD
ns
TBD
TBD
TBD
TBD
ns
ns
Table 18: Read operation from Intel-type Local Bus
Symbol
t
ref
t
za
t
awr
t
zwcs1
t
zwcs2
t
cswr
t
wrcs
t
zwr1
t
zwr2
t
zdv
t
zdf
t
wrdi
Parameter
IRDY# falling to reference LBCLK
Reference LBCLK to Address Valid
Address Valid to LBWR# falling
Reference LBCLK to LBCS# falling
Reference LBCLK to LBCS# rising
LBCS# falling to LBWR# falling
LBWR# rising to LBCS# rising
Reference LBCLK to LBWR# falling
Reference LBCLK to LBWR# rising
Reference LBCLK to data bus valid
Reference LBCLK to data bus high-impedance
LBWR# rising to data bus invalid
Min
Nominally 2 PCI clock cycles
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 19: Write operation to Intel-type Local Bus
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