參數(shù)資料
型號(hào)： OX9162
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Parallel Port/Local Bus and PCI interface
中文描述： 綜合并口/本地總線(xiàn)和PCI接口
文件頁(yè)數(shù)： 16/41頁(yè)
文件大?。?/td> 347K
代理商： OX9162
Data Sheet Revision 1.1 PRELIMINARY
Page 16
OX9162
OXFORD SEMICONDUCTOR LTD.
4.4.5
Global Interrupt Status and Control Register ‘GIS’ (Offset 0x10)
Bits
1:0
2
Description
Reserved
MIO0 This bit reflects the state of the internal MIO[0]. The internal MIO[0]
reflects the non-inverted or inverted state of MIO0 pin.
MIO1 This bit reflects the state of the internal MIO[0]. The internal MIO[0]
reflects the non-inverted or inverted state of MIO0 pin.
Reserved
MIO0 INTA enable
When set (1) allows MIO0 to assert a PCI interrupt on the INTA line. State of
MIO0 that causes an interrupt is dependant upon the polarity set by MIC(1:0)
MIO1 INTA enable
When set (1) allows MIO1 to assert a PCI interrupt on the INTA line. State of
MIO1 that causes an interrupt is dependant upon the polarity set by MIC(3:2)
Power-down Interrupt This is a sticky bit. When set, it indicates a power-down
request issued and would normally have asserted a PCI interrupt if bit 21 was
set (see section 7.9). Reading this bit clears it.
Power-down interrupt enable. When ‘1’ a power down request is allowed to
generate an interrupt.
Parallel Port Mode only : Parallel port interrupt status
Parallel Port Mode only : Parallel port interrupt enable
Read/Write
EEPROM
-
-
-
-
W
Reset
PCI
R
R
0x0h
X
3
R
X
17-4
18
R
RW
0
1 for local bus
mode
0 for parallel port
1 for local bus
mode
0 for parallel port
X
19
W
RW
20
-
R
21
W
RW
0
22
23
-
W
R
RW
0
1 for parallel port
mode
0 for local bus
000h
31:24
Reserved
-
R
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