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參數(shù)資料
| 型號： | OX9162 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Parallel Port/Local Bus and PCI interface |
| 中文描述： | 綜合并口/本地總線和PCI接口 |
| 文件頁數(shù)： | 14/41頁 |
| 文件大?。?/td> | 347K |
| 代理商： | OX9162 |
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Data Sheet Revision 1.1 PRELIMINARY
Page 14
OX9162
OXFORD SEMICONDUCTOR LTD.
Bits
Description
These bits are unused in Motorola-type interface.
Write Chip-select De-assertion (Intel-type interface). Defines the number
of clock cycles after the reference cycle when the LBCS[1:0]# pins are
de-asserted (high) during a write operation to the Local Bus.
1
Read-not-Write De-assertion during write cycles (Motorola-type
interface). Defines the number of clock cycles after the reference cycle
when the LBRDWR# pin is de-asserted (high) during a write to the Local
Bus.
1
Read Control Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBRD# pin is asserted
(low) during a read from the Local Bus.
1
Read Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[1:0]#
pins are asserted (low) during a read from the Local Bus.
1
Read Control De-assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBRD# pin is de-
asserted (high) during a read from the Local Bus.
1
Read Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[1:0]#
pins are de-asserted (high) during a read from the Local Bus.
1
Write Control Assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBWR# pin is asserted
(low) during a write to the Local Bus.
1
Write Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[1:0]#
pins are asserted (low) during a write to the Local Bus.
1
Write Control De-assertion (Intel-type interface). Defines the number of
clock cycles after the Reference Cycle when the LBWR# pin is de-
asserted (high) during a write to the Local Bus.
1
Write Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[1:0]#
pins are de-asserted (high) during a write cycle to the Local Bus.
1
Read/Write
EEPROM
Reset
PCI
15:12
W
RW
2h
19:16
W
RW
0h
(1h for
parallel port)
23:20
W
RW
3h
(2h for
parallel port)
27:24
W
RW
0h
(1h for
parallel port)
31:28
W
RW
2h
Note 1:
Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. See notes in the following page.
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