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| 型號： | OX9162 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Integrated Parallel Port/Local Bus and PCI interface |
| 中文描述： | 綜合并口/本地總線和PCI接口 |
| 文件頁數(shù)： | 22/41頁 |
| 文件大小： | 347K |
| 代理商： | OX9162 |
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6.3
Data Sheet Revision 1.1 PRELIMINARY
Page 22
OX9162
OXFORD SEMICONDUCTOR LTD.
Register Description
The parallel port registers are described below. (NB it is assumed that the upper block is placed 400h above the lower block).
Register
Name
Offset
SPP (Compatibility Mode) Registers
PDR
000h
R/W
ecpAFifo
000h
R/W
DSR
(EPP mode)
(Other modes)
001h
R
nBUSY
ACK#
DCR
002h
R/W
0
0
EPPA
1
003h
R/W
EPPD1
1
004h
R/W
EPPD2
1
005h
R/W
EPPD3
1
006h
R/W
EPPD4
1
007h
R/W
EcpDFifo
400h
R/W
TFifo
400h
R/W
CnfgA
400h
R
CnfgB
401h
R
0
int
ECR
402h
R/W
Mode[2:0]
-
403h
-
Address
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Parallel Port Data Register
ECP FIFO : Address / RLE
SLCT
001h
R
nBUSY
ACK#
PE
ERR#
INT#
1
Timeout
PE
DIR
SLCT
INT_EN
EPP Address Register
EPP Data 1 Register
EPP Data 2 Register
EPP Data 3 Register
EPP Data 4 Register
ECP Data FIFO
Test FIFO
Configuration A Register – always 90h
ERR#
nSLIN#
INT#
INIT#
1
1
nAFD#
nSTB#
‘000000’
Must write ‘00001’
Reserved
Table 7: Parallel port register set
Note 1 : These registers are only available in EPP mode.
Note 2 : Prefix ‘n’ denotes that a signal is inverted at the connector. Suffix ‘#’ denotes active-low signalling
The reset state of PDR, EPPA and EPPD1-4 is not determinable (i.e. 0xXX). The reset value of DSR is ‘XXXXX111’. DCR and
ECR are reset to ‘0000XXXX’ and ‘00000001’ respectively.
6.3.1
PDR is located at offset 000h in the lower block. It is the
standard parallel port data register. Writing to this register
in mode 000 will drive data onto the parallel port data lines.
In all other modes the drivers may be tri-stated by setting
the direction bit in the DCR. Reads from this register return
the value on the data lines.
Parallel port data register ‘PDR’
6.3.2
A data byte written to this address will be interpreted as an
address if bit(7) is set, otherwise an RLE count for the next
data byte. Count = bit(6:0) + 1.
ECP FIFO Address / RLE
6.3.3
DSR is located at offset 001h in the lower block. It is a read
only register showing the current state of control signals
from the peripheral. Additionally in EPP mode, bit 0 is set
to ‘1’ when an operation times out (see section 6.1.3)
DSR[0]:
EPP mode: Timeout
logic 0
Timeout has not occurred.
logic 1
Timeout has occurred (Reading this bit clears it).
Other modes: Unused
This bit is permanently set to 1.
DSR[1]: Unused
This bit is permanently set to 1.
Device status register ‘DSR’
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