參數(shù)資料
型號： OX9162
廠商： Electronic Theatre Controls, Inc.
英文描述： Integrated Parallel Port/Local Bus and PCI interface
中文描述： 綜合并口/本地總線和PCI接口
文件頁數(shù)： 2/41頁
文件大?。?/td> 347K
代理商： OX9162
Data Sheet Revision 1.1 PRELIMINARY
Page 2
OX9162
OXFORD SEMICONDUCTOR LTD.
C
ONTENTS
1
2
3
4
4.1
4.2
4.2.1
MAP
4.3
4.3.1
4.3.2
4.4
REGISTERS........................................................................12
4.4.1
LOCAL CONFIGURATION AND CONTROL
REGISTER ‘LCC’ (OFFSET 0X00)....................................12
4.4.2
MULTI-PURPOSE I/O CONFIGURATION
REGISTER ‘MIC’ (OFFSET 0X04).....................................13
4.4.3
LOCAL BUS TIMING PARAMETER REGISTER
1 ‘LT1’ (OFFSET 0X08):.....................................................13
4.4.4
LOCAL BUS TIMING PARAMETER/BAR
SIZING REGISTER 2 ‘LT2’ (OFFSET 0X0C):...................15
4.4.5
GLOBAL INTERRUPT STATUS AND
CONTROL REGISTER ‘GIS’ (OFFSET 0X10).................16
4.5
PCI INTERRUPTS.................................................17
4.6
POWER MANAGEMENT......................................18
4.6.1
POWER MANAGEMENT USING MIO............18
5
LOCAL BUS ...........................................19
5.1
OVERVIEW............................................................19
5.2
OPERATION..........................................................19
5.3
CONFIGURATION & PROGRAMMING..............20
6
BI-DIRECTIONAL PARALLEL PORT......21
6.1
OPERATION AND MODE SELECTION..............21
6.1.1
SPP MODE........................................................21
6.1.2
PS2 MODE........................................................21
6.1.3
EPP MODE........................................................21
6.1.4
ECP MODE........................................................21
6.2
PARALLEL PORT INTERRUPT..........................21
PIN INFORMATION...................................3
PIN DESCRIPTIONS.................................4
CONFIGURATION & OPERATION............8
PCI TARGET CONTROLLER....................9
OPERATION............................................................9
CONFIGURATION SPACE....................................9
PCI CONFIGURATION SPACE REGISTER
10
ACCESSING LOGICAL FUNCTIONS.................11
PCI ACCESS TO 8-BIT LOCAL BUS..............11
PCI ACCESS TO PARALLEL PORT...............11
ACCESSING LOCAL CONFIGURATION
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
7
7.1
7.2
7.2.1
7.2.2
REGISTERS........................................................................27
7.2.3
ZONE2: IDENTIFICATION REGISTERS........28
7.2.4
ZONE3: PCI CONFIGURATION REGISTERS28
7.2.5
ZONE4: FUNCTION ACCESS.........................28
8
OPERATING CONDITIONS.....................30
9
DC ELECTRICAL CHARACTERISTICS..30
9.1
NON-PCI I/O BUFFERS.......................................30
9.2
PCI I/O BUFFERS.................................................31
10
AC ELECTRICAL CHARACTERISTICS
32
10.1
PCI BUS................................................................32
10.2
LOCAL BUS..........................................................32
11
TIMING WAVEFORMS........................34
12
ERRATA 1 – IMMEDIATE POWER
DOWN FILTERING.........................................39
REGISTER DESCRIPTION..................................22
PARALLEL PORT DATA REGISTER ‘PDR’...22
ECP FIFO ADDRESS / RLE............................22
DEVICE STATUS REGISTER ‘DSR’..............22
DEVICE CONTROL REGISTER ‘DCR’...........23
EPP ADDRESS REGISTER ‘EPPA’...............23
EPP DATA REGISTERS ‘EPPD1-4’...............23
ECP DATA FIFO...............................................23
TEST FIFO........................................................23
CONFIGURATION A REGISTER....................23
CONFIGURATION B REGISTER....................24
EXTENDED CONTROL REGISTER ‘ECR’....24
SERIAL EEPROM...................................25
SPECIFICATION...................................................25
EEPROM DATA ORGANISATION......................25
ZONE0: HEADER.............................................25
ZONE1: LOCAL CONFIGURATION
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