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參數(shù)資料
| 型號： | ORT8850 |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 8/112頁 |
| 文件大小： | 2417K |
| 代理商： | ORT8850 |
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8
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Description
(continued)
Following design entry, the development system
’
s map,
place, and route tools translate the netlist into a routed
FPGA. A floorplanner is available for layout feedback
and control. A static timing analysis tool is provided to
determine device speed and a back-annotated netlist
can be created to allow simulation and timing.
Timing and simulation output files from
ORCA
Foundry
are also compatible with many third-party analysis
tools. Its bit stream generator is then used to generate
the configuration data which is loaded into the FPGAs
internal configuration RAM, embedded block RAM,
and/or FPSC memory.
When using the bit stream generator, the user selects
options that affect the functionality of the FPGA. Com-
bined with the front-end tools,
ORCA
Foundry pro-
duces configuration data that implements the various
logic and routing options discussed in this data sheet.
FPSC Design Kit
Development is facilitated by an FPSC design kit
which, together with
ORCA
Foundry and third-party
synthesis and simulation engines, provides all software
and documentation required to design and verify an
FPSC implementation. Included in the kit are the FPSC
configuration manager,
Synopsys Smart Model
, and
complete online documentation. The kit's software cou-
ples with
ORCA
Foundry, providing a seamless FPSC
design environment. More information can be obtained
by visiting the
ORCA
website or contacting a local
sales office, both listed on the last page of this docu-
ment.
FPGA Logic Overview
The
ORCA
Series 4 architecture is a new generation of
SRAM-based programmable devices from Agere. It
includes enhancements and innovations geared
toward today
’
s high-speed systems on a single chip.
Designed with networking applications in mind, the
Series 4 family incorporates system-level features that
can further reduce logic requirements and increase
system speed.
ORCA
Series 4 devices contain many
new patented enhancements and are offered in a vari-
ety of packages and speed grades.
The hierarchical architecture of the logic, clocks, rout-
ing, RAM, and system-level blocks create a seamless
merge of FPGA and ASIC designs. Modular hardware
and software technologies enable system-on-chip inte-
gration with true plug-and-play design implementation.
The architecture consists of four basic elements: pro-
grammable logic cells (PLCs), programmable I/O cells
(PIOs), embedded block RAMs (EBRs), and system-
level features. These elements are interconnected with
a rich routing fabric of both global and local wires. An
array of PLCs are surrounded by common interface
blocks which provide an abundant interface to the adja-
cent PLCs or system blocks. Routing congestion
around these critical blocks is eliminated by the use of
the same routing fabric implemented within the pro-
grammable logic core. Each PLC contains a PFU,
SLIC, local routing resources, and configuration RAM.
Most of the FPGA logic is performed in the PFU, but
decoders,
PAL
-like functions, and 3-state buffering can
be performed in the SLIC. The PIOs provide device
inputs and outputs and can be used to register signals
and to perform input demultiplexing, output multiplex-
ing, uplink and downlink functions, and other functions
on two output signals. Large blocks of 512 x 18 quad-
port RAM complement the existing distributed PFU
memory. The RAM blocks can be used to implement
RAM, ROM, FIFO, multiplier, and CAM. Some of the
other system-level functions include the MPI, PLLs,
and the embedded system bus (ESB).
PLC Logic
Each PFU within a PLC contains eight 4-input (16-bit)
LUTs, eight latches/FFs, and one additional flip-flop
that may be used independently or with arithmetic func-
tions.
The PFU is organized in a twin-quad fashion; two sets
of four LUTs and FFs that can be controlled indepen-
dently. Each PFU has two independent programmable
clocks, clock enables, local set/reset, and data selects.
LUTs may also be combined for use in arithmetic func-
tions using fast-carry chain logic in either 4-bit or 8-bit
modes. The carry-out of either mode may be registered
in the ninth FF for pipelining. Each PFU may also be
configured as a synchronous 32 x 4 single- or dual-port
RAM or ROM. The FFs (or latches) may obtain input
from LUT outputs or directly from invertible PFU inputs,
or they can be tied high or tied low. The FFs also have
programmable clock polarity, clock enables, and local
set/reset.
相關PDF資料 |
PDF描述 |
|---|---|
| ORT8850H | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850L | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| OS1001 | Interface IC |
| OS1010 | Optoelectronic |
| OS1011 | SINGLE 1.8V, 200 KHZ OP, E TEMP, -40C to +125C, 8-PDIP, TUBE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850H | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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