參數(shù)資料
型號： ORT8850
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 2/112頁
文件大?。?/td> 2417K
代理商： ORT8850
Table of Contents
Contents
Page
Contents
Page
2
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Introduction..................................................................1
Embedded Core Features (Serial)...............................4
Embedded Core Features (Parallel)............................4
Programmable FPGA Features...................................5
Programmable Logic System Features.......................6
Description...................................................................7
What Is an FPSC ...................................................7
FPSC Overview .......................................................7
FPSC Gate Counting ...............................................7
FPGA/Embedded Core Interface .............................7
ORCA
Foundry Development System .....................7
FPSC Design Kit ......................................................8
FPGA Logic Overview ..............................................8
PLC Logic ................................................................8
Programmable I/O ....................................................9
Routing .....................................................................9
System-Level Features..............................................10
Microprocessor Interface .......................................10
System Bus ............................................................10
Phase-Locked Loops .............................................10
Embedded Block RAM ...........................................10
Configuration ..........................................................11
Additional Information ............................................11
ORT8850 Overview...................................................12
Device Layout ........................................................12
Backplane Transceiver Interface ...........................12
HSI Interface ..........................................................15
STM Macrocell .......................................................15
8B/10B Encoder/Decoder ......................................15
FPGA Interface ......................................................15
Byte-Wide Parallel Interface ..................................15
FPSC Configuration ...............................................16
Generic Backplane Transceiver Application..............17
Synchronous Transfer Mode (STM) .......................17
8B/10B Mode .........................................................17
Backplane Transceiver Core Detailed Description....18
HSI Macro ..............................................................18
STM Transmitter (FPGA
Backplane) .................20
STM Receiver (Backplane
FPGA) .....................23
8B/10B Transmitter (FPGA
Backplane) ............30
8B/10B Receiver (Backplane
FPGA) ................30
Pointer Mover Block (Backplane
FPGA) ...........31
Receive Bypass Options and FPGA Interface .......33
Powerdown Mode ................................................. 33
STM Redundancy and Protection Switching ......... 33
LVDS Protection Switching ................................... 34
RapidIO
Interface to Pi-Sched.................................. 34
Overview ............................................................... 34
Receive Cell Interface ........................................... 34
Transmit Cell Interface .......................................... 36
Memory Map............................................................. 38
Definition of Register Types .................................. 38
Absolute Maximum Ratings...................................... 55
Recommended Operating Conditions ...................... 55
Power Supply Decoupling LC Circuit........................ 56
HSI Electrical and Timing Characteristics ................ 57
Parallel
RapidIO
-like Interface Timing
Characteristics......................................................... 58
Embedded Core LVDS I/O ....................................... 59
LVDS Receiver Buffer Requirements .................... 60
Input/Output Buffer Measurement Conditions
(on-LVDS Buffer)..................................................... 61
LVDS Buffer Characteristics..................................... 62
Termination Resistor ............................................. 62
LVDS Driver Buffer Capabilities ............................ 62
Pin Information ......................................................... 63
Package Pinouts ................................................... 77
Package Thermal Characteristics Summary .......... 105
Θ
JA ..................................................................... 105
Ψ
JC ..................................................................... 105
Θ
JC ..................................................................... 105
Θ
JB ..................................................................... 105
FPSC Maximum Junction Temperature .............. 105
Package Thermal Characteristics........................... 106
Package Coplanarity .............................................. 106
Package Parasitics................................................. 106
Package Outline Diagrams..................................... 107
Terms and Definitions ......................................... 107
Package Outline Drawings..................................... 108
352-Pin PBGA ..................................................... 108
680-Pin PBGAM .................................................. 109
Hardware Ordering Information.............................. 110
Software Ordering Information ............................... 111
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ORT8850-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓:
ORT8850H 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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