參數(shù)資料
型號: ORT8850
英文描述: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述: 現(xiàn)場可編程系統(tǒng)芯片(促進文化基金)8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù): 11/112頁
文件大?。?/td> 2417K
代理商: ORT8850
Agere Systems Inc.
11
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
System-Level Features
(continued)
Configuration
The FPGAs functionality is determined by internal con-
figuration RAM. The FPGAs internal initialization/con-
figuration circuitry loads the configuration data at
powerup or under system control. The configuration
data can reside externally in an EEPROM or any other
storage media. Serial EEPROMs provide a simple, low
pin-count method for configuring FPGAs.
The RAM is loaded by using one of several configura-
tion modes. Supporting the traditional master/slave
serial, master/slave parallel, and asynchronous periph-
eral modes, the Series 4 also utilizes its microproces-
sor interface and embedded system bus to perform
both programming and readback. Daisy chaining of
multiple devices and partial reconfiguration are also
permitted.
Other configuration options include the initialization of
the embedded-block RAM memories and FPSC mem-
ory as well as system bus options and bit stream error
checking. Programming and readback through the
JTAG
(IEEE
1149.2
)
port is also available meeting in-
system programming (ISP) standards (
IEEE
1532
Draft).
Additional Information
Contact your local Agere representative for additional
information regarding the
ORCA
Series 4 FPGA
devices, or visit our website at:
http://www.agere.com/orca
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