參數(shù)資料
型號(hào)： ORT8850
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù)： 69/112頁(yè)
文件大?。?/td> 2417K
代理商： ORT8850
Agere Systems Inc.
69
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Pin Information
(continued)
Table 30. FPSC Function Pin Description
(continued)
Symbol
I/O
Description
RapidIO
LVDS Interface Pins (Transmitter)
txd_a_p<7:0>
txd_a_n<7:0>
txsoc_a_p
txsoc_a_n
txclk_a_p
txclk_a_n
txd_b_p<7:0>
txd_b_n<7:0>
txsoc_b_p
txsoc_b_n
txclk_b_p
txclk_b_n
txd_c_p<7:0>
txd_c_n<7:0>
txsoc_c_p
txsoc_c_n
txclk_c_p
txclk_c_n
MISC System Signals
rst_n
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
LVDS data for
RapidIO
, transmitter port A.
LVDS data for
RapidIO
, transmitter port A.
LVDS start-of-cell for
RapidIO
, transmitter port A.
LVDS start-of-cell for
RapidIO
, transmitter port A.
LVDS receive clock for
RapidIO
, transmitter port A.
LVDS receive clock for
RapidIO
, transmitter port A.
LVDS data for
RapidIO
, transmitter port B.
LVDS data for
RapidIO
, transmitter port B.
LVDS start-of-cell for
RapidIO
, transmitter port B.
LVDS start-of-cell for
RapidIO
, transmitter port B.
LVDS receive clock for
RapidIO
, transmitter port B.
LVDS receive clock for
RapidIO
, transmitter port B.
LVDS data for
RapidIO
, transmitter port C.
LVDS data for
RapidIO
, transmitter port C.
LVDS start-of-cell for
RapidIO
, transmitter port C.
LVDS start-of-cell for
RapidIO
, transmitter port C.
LVDS receive clock for
RapidIO
, transmitter port C.
LVDS receive clock for
RapidIO
, transmitter port C.
I
Reset the core only. The FPGA logic is not reset by rst_n.
Internal pull down allows chip to stay in reset state when external driver
loses power.
LVDS system clock, 50% duty cycle, also the reference clock of PLL.
LVDS system clock, 50% duty cycle, also the reference clock of PLL.
LVDS clock for
RapidIO
PLL internal pull-up.
LVDS clock for
RapidIO
PLL internal pull-up.
Temperature-sensing diode (anode +).
Temperature-sensing diode (cathode
–
).
LVDS center-tap for sys_clk (use 0.01 μf to GND).
LVDS center-tap for gclk (use 0.01 μf to GND).
sys_clk_p
sys_clk_n
gclk_p
gclk_n
dxp
dxn
lvctap_sk
lvctap_gk
I
I
I
I
—
—
O
O
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ORT8850-FPSC-EV 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產(chǎn)品:Development Kits 類型:FPGA 工具用于評(píng)估:5CEFA7F3 接口類型: 工作電源電壓:
ORT8850H 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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