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參數(shù)資料
| 型號： | ORT8850 |
| 英文描述： | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| 中文描述： | 現(xiàn)場可編程系統(tǒng)芯片（促進文化基金）8通道x 850 Mbits /秒背板收發(fā)器 |
| 文件頁數(shù)： | 16/112頁 |
| 文件大?。?/td> | 2417K |
| 代理商： | ORT8850 |
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16
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
ORT8850 Overview
(continued)
FPSC Configuration
Configuration of the ORT8850 occurs in two stages:
FPGA bit stream configuration and embedded core
setup.
FPGA Configuration
Prior to becoming operational, the FPGA goes through
a sequence of states, including powerup, initialization,
configuration, start-up, and operation. The FPGA logic
is configured by standard FPGA bit stream configura-
tion means as discussed in the Series 4 FPGA data
sheet. The options for the embedded core are set via
registers that are accessed through the FPGA system
bus. The system bus can be driven by an external PPC
compliant microprocessor via the MPI block or via a
user master interface in FPGA logic. A simple IP block,
that drives the system by using the user interface and
uses very little FPGA logic, is available in the
MPI/Sys-
tem Bus
application note (AP01-032NCIP). This IP
block sets up the embedded core via a state machine
and allows the ORT8850 to work in an independent
system without an external microprocessor interface.
Embedded Core Setup
All options for the operation of the core are configured
according to the device register map, which is included
with the ORT8850 FPSC simulation kit.
During the powerup sequence, the ORT8850 device
(FPGA programmable circuit and the core) is held in
reset. All the LVDS output buffers and other output
buffers are held in 3-state. All flip-flops in the core area
are in reset state, with the exception of the boundry-
scan shift registers, which can only be reset by bound-
ary-scan reset. After powerup reset, the FPGA can
start configuration. During FPGA configuration, the
ORT8850 core will be held in reset and all the local bus
interface signals forced high, but the following active-
high signals (PROT_SWITCH_A, PROT_SWITCH_C,
TX_TOH_CK_EN, SYS_FP, LINE_FP) will be forced
low. The CORE_READY signal sent from the embed-
ded core to FPGA is held low, indicating that the core is
not ready to interact with FPGA logic. At the end of the
FPGA configuration sequence, the CORE_READY sig-
nal will be held low for six SYS_CLK cycles after
DONE, TRI_IO and RST_N (core global reset) are
high. Then it will go active-high, indicating the embed-
ded core is ready to function and interact with FPGA
programmable circuit. During FPGA reconfiguration
when DONE and TRI_IO are low, the CORE_READY
signal sent from the core to FPGA will be held low
again to indicate the embedded core is not ready to
interact with FPGA logic. During FPGA partial configu-
ration, CORE_READY stays active. The same FPGA
configuration sequence described previously will
repeat again.
The initialization of the embedded core consists of two
steps: register configuration and synchronization of the
alignment FIFO. In order to configure the embedded
core, the registers need to be unlocked by writing
0x30005 to address 0x30004 and writing 0x80 to
address 0x05. Control registers 0x30004 and 0x30005
are lock registers. If the output bus of the data, serial
TOH port, and TOH clock and TOH frame pulse are
controlled by 3-state registers (the use of the registers
for 3-state output control is optional; these output 3-
state enable signals are brought across the local bus
interface and available to the FPGA side), the next step
is to activate the 3-state output bus and signals by tak-
ing them to functional state from high-impedance state.
This can be done by writing 0x01 to correspond bits of
the channel registers 0x30020, 0x30038, 0x30050,
0x30068, 0x30080, 0x30090, 0x300B0, and 0x300C8.
In addition, the synchronization of selected streams is
recommended for some networking systems applica-
tions. This requires a resync of the alignment FIFO
after the enabled channels have a valid frame pulse or
8B/10B control character. See the sections about STM
Link Alignment Setup or 8B/10B Link Alignment Setup
for more details.
相關PDF資料 |
PDF描述 |
|---|---|
| ORT8850H | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850L | Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| OS1001 | Interface IC |
| OS1010 | Optoelectronic |
| OS1011 | SINGLE 1.8V, 200 KHZ OP, E TEMP, -40C to +125C, 8-PDIP, TUBE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ORT8850-FPSC-EV | 功能描述:可編程邏輯 IC 開發(fā)工具 ORCA ORT8850 FPSC Eval Brd RoHS:否 制造商:Altera Corporation 產品:Development Kits 類型:FPGA 工具用于評估:5CEFA7F3 接口類型: 工作電源電壓: |
| ORT8850H | 制造商:AGERE 制造商全稱:AGERE 功能描述:Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver |
| ORT8850H-1BM680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BM680I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| ORT8850H-1BMN680C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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