參數(shù)資料
型號(hào): ORT8850
英文描述: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述: 現(xiàn)場(chǎng)可編程系統(tǒng)芯片(促進(jìn)文化基金)8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù): 51/112頁
文件大小: 2417K
代理商: ORT8850
Agere Systems Inc.
51
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Memory Map
(continued)
Table 12. Memory Map Descriptions
(continued)
Bit/Register Name(S)
Bit/Register
Location (Hex)
Register
Type
Reset
Value
(Hex)
0
Description
FIFO aligner threshold
error flag
receiver internal path par-
ity error flag
LOF flag
LVDS link B1 parity error
flag
input parallel bus parity
error flag
TOH serial input port par-
ity error flag
FIFO OOS error flag
enable/mask register [0:5]
28, 40, 58, 70,
88, a0, b8, d0 [0]
28, 40, 58, 70,
88, a0, b8, d0 [1]
28, 40, 58, 70,
88, a0, b8, d0 [2]
28, 40, 58, 70,
88, a0, b8, d0 [3]
28, 40, 58, 70,
88, a0, b8, d0 [4]
28, 40, 58, 70,
88, a0, b8, d0 [5]
28, 40, 58, 70,
88, a0, b8, d0 [6]
29, 41, 59, 71,
89, a1, b9, d1
[0:5]
iareg
iareg
iareg
iareg
iareg
iareg
iereg
0
0
0
0
0
00
These are the per STS-12 alarm flags.
Loss of frame.
FIFO out of Sysc error flag.
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