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參數(shù)資料
| 型號： | NCP4330DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | MOSFETs |
| 英文描述： | Post Regulation Driver |
| 中文描述： | BUF OR INV BASED MOSFET DRIVER, PDSO8 |
| 封裝： | LEAD FREE, DSO-8 |
| 文件頁數(shù)： | 9/18頁 |
| 文件大?。?/td> | 123K |
| 代理商： | NCP4330DR2G |
NCP4330
http://onsemi.com
9
DETAILED OPERATING DESCRIPTION
Introduction
The NCP4330 is designed for forward, multiple output
power supplies using synchronous rectification. One output
is traditionally regulated thanks to a regulation arrangement
that modulates the forward converter duty cycle. The other
outputs are regulated by a dual MOSFET arrangement
driven by the NCP4330. The highside MOSFET turns on
during one part of the forward converter ontime, while the
lowside power switch is ON for the rest of the period (free
wheeling).
The sequencing of the switching phases, includes
overlaps that result in only one hard switching (highside
turn on). The three other transitions are soft for an optimum
efficiency.
The synchronous rectification enables to keep a
Continuous Conduction Mode (CCM) operation whatever
the load is, as this technique allows to send back some
energy towards the input (light load conditions). In
Continuous Conduction Mode (CCM), the forward duty
cycle is simply given by the following equation:
Vout1
(ns
df
np) * Vin
where: d
f
is the forward duty cycle,
n
s
/n
p
is the transformer turn ratio (n
p
: primary
number of turns, n
s
: secondary number of turns),
Vin is the forward converter input voltage,
Vout1 is the main output voltage of the forward
converter.
The postregulated output voltages are given by the
following equation:
dn*np* Vin,
Voutn
where d
n
is the duty cycle of the postregulator n, with
d
n
< d
f
since (n
s
*Vin/n
p
) is available only during the
forward converter ontime.
Postregulated output voltages are then necessarily lower
than the main regulated one.
Sequencing and Regulation Block
The timing diagram of page 2 portrays the phases
sequencing.
Typically, a regulation arrangement injects a current into
pin 5, in order to adjust the highside MOSFET duty cycle.
Pin 5 current is internally mirrored in order to charge the
C
ramp
capacitor. An internal comparator (1.0 V hysteresis)
detects when the capacitor voltage exceeds the 2.5 V internal
reference. At that moment, the lowside MOSFET turns off.
100 ns later (typically), the high–side MOSFET switches on
and keeps on until (following the turn off of the forward
converter power switch) a RESET signal is applied to pin 3.
At that time, an internal switch grounds the C
ramp
pin and
abruptly discharges the C
ramp
capacitor. As a consequence,
the internal comparator turns low and forces the lowside
MOSFET on. The highside MOSFET turns off 100 ns later.
During the 100 ns during which both high and low side
MOSFETs are on, the MOSFET Q1 of the application
schematic is off and no energy can then be drawn from the
converter transformer. Therefore, these 100 ns should not be
considered as a part of the highside MOSFET conduction
time which can be computed as follows:
ton_HS
Tsw
tRST
tLS,HS
tcharge
where: T
sw
is the forward switching period,
t
RST
is the C
ramp
reset time during which the
capacitor is kept grounded,
t
LS,HS
is the delay between the lowside turn off
and the highside switch on. During this time,
100 ns typically, the two drivers are in low state,
t
charge
is the time necessary to charge the C_ramp
capacitor up to the 2.5 V reference voltage.
Given that:
Cramp* Vref
tcharge
Iramp
where: C
ramp
is the capacitor connected to the C_ramp
pin,
I
ramp
is the current injected into the I_ramp pin,
Vref is the 2.5 V reference voltage,
the following equation dictates the highside MOSFET duty
cycle:
don_HS
1
tRST
tLS,HS
Tsw
Cramp*Vref
Iramp
The following curve gives d
on_HS
versus the current I
ramp
in the following conditions: 400 kHz switching frequency,
250 ns reset pulse duration, 100 ns switching delay (between
LS and HS), 100 pF C
ramp
capacitor.
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