參數(shù)資料
型號: NCP4330DR2G
廠商: ON SEMICONDUCTOR
元件分類: MOSFETs
英文描述: Post Regulation Driver
中文描述: BUF OR INV BASED MOSFET DRIVER, PDSO8
封裝: LEAD FREE, DSO-8
文件頁數(shù): 11/18頁
文件大小: 123K
代理商: NCP4330DR2G
NCP4330
http://onsemi.com
11
LowSide Driver Stage
The timing diagram of page 2 portrays the sequencing
driven by the NCP4330.
The lowside drive is controlled by an internal
comparator that compares the C_ramp voltage to the internal
reference 2.5 V (1.0 V hysteresis). When the C_ramp
exceeds the 2.5 V reference, the comparator turns high
forcing the lowside MOSFET off. 100 ns later, the
highside MOSFET switches on.
When a reset signal is applied to the reset pin, the C_ramp
capacitor is grounded. As a consequence, the internal
comparator turns low and forces the lowside MOSFET on.
100 ns later, the highside MOSFET switches off.
The lowside drive is designed to drive on and off a 25 nC
gate charge power MOSFET, in 25 ns typical.
1. LowSide MOSFET Turn On:
In nominal operation, the body diode is already ON when
the lowside MOSFET turns on. The energy Qg to be
supplied is then approximately half the energy necessary if
the drain source voltage was high.
The necessary current capability is then:
1
2*25 nC
Ils
on
25 ns
, that is 500 mA.
Figure 28. LowSide MOSFET Turn ON
4.5010 M
4.5015 M
4.5020 M
Time in Secs
4.5025 M
4.5030 M
40.0
20.0
0
20.0
40.0
l
0
4.00
8.00
12.0
16.0
i
1.50
500 M
2.50
4.50
6.50
i
320
240
160
80.0
0
v
0
20.0
40.0
60.0
80.0
v
vin1
i(l1)
v(vsn)
irl
ls_drv
Vin
lind
LS_DRV
I
Q
V
Q
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