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參數(shù)資料
| 型號(hào)： | NCP4330DR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類(lèi)： | MOSFETs |
| 英文描述： | Post Regulation Driver |
| 中文描述： | BUF OR INV BASED MOSFET DRIVER, PDSO8 |
| 封裝： | LEAD FREE, DSO-8 |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大?。?/td> | 123K |
| 代理商： | NCP4330DR2G |
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NCP4330
http://onsemi.com
2
Figure 2. Timing Diagram(s)
Converter Winding
Voltage
C_ramp Voltage
HighSide Driver
(referenced to
HS MOSFET source)
LowSide Driver
100 ns delay
VrefH
VrefL
Time
Time
Time
Time
0 V
0 V
Time
Synchronization
Signal
Time
Internal RESET
Signal
100 ns delay
2.55 V
DETAILED PIN DESCRIPTION(S)
Pin
Number
Name
Function
1
HS_DRV
“HS_DRV” is the gate driver of the highside MOSFET.
2
BST
“BST” is the bootstrap pin. A 0.1 F to 1.0 F ceramic capacitor should be connected between this pin
and the node that is common to the coil and the two MOSFET. The “BST” voltage feeds the highside
driver (“HS_DRV”).
3
RST
The “RST” pin resets the C_ramp voltage in order to synchronize the postregulator freewheeling
sequence to the forward converter demagnetization phase.
4
C_ramp
The capacitor connected to the C_ramp pin enables to adjust the delay in turning on the highside
MOSFET (in conjunction with “I_ramp” current).
5
I_ramp
The “I_ramp” pin receives a current supplied by a regulation means. This current adjusts the delay after
which the highside MOSFET is turned on. By this way, it modules the highside MOSFET on time in
order to regulate the output voltage.
6
V
DD
“V
DD
” is the power supply input. A 0.1 F to 1.0 F ceramic capacitor should be connected from this pin
to ground for decoupling.
7
LS_DRV
“LS_DRV” is the driver output of the lowside MOSFET gate.
8
GND
Ground.
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