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參數(shù)資料
| 型號： | NAND256W4A2AZA6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55 |
| 文件頁數(shù)： | 7/58頁 |
| 文件大?。?/td> | 1406K |
| 代理商： | NAND256W4A2AZA6E |
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NAND128-A, NAND256-A
Signal descriptions
15/58
3
Signal descriptions
See Figure 1: Logic diagram and Table 3: Signal names for a brief overview of the signals
connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/Outputs 0 to 7 input the selected address, output the data during a read operation or
input a command or data during a write operation. The inputs are latched on the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are
disabled.
3.2
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They output the data during a read
operation or input data during a write operation. Command and address inputs only require
I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
Address Latch Enable (AL)
Address Latch Enable activates the latching of the address inputs in the command interface.
When AL is high, the inputs are latched on the rising edge of Write Enable.
3.4
Command Latch Enable (CL)
The Command Latch Enable activates the latching of the command inputs in the command
interface. When CL is high, the inputs are latched on the rising edge of Write Enable.
3.5
Chip Enable (E)
The Chip Enable input activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, VIL, the device is selected.
While the device is busy programming or erasing, Chip Enable transitions to High (VIH) are
ignored and the device does not go into standby mode.
While the device is busy reading:
●
the Chip Enable input should be held Low during the whole busy time (tBLBH1) for
devices that do not feature the Chip Enable don’t care option. Otherwise, the read
operation in progress is interrupted and the device goes into standby mode.
●
for devices that feature the Chip Enable don’t care option, the Chip Enable going High
during the busy time (tBLBH1) will not interrupt the read operation and the device will not
go into standby mode.
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| NAND32GAH0HZA5E | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Trays |
| NAND32GAH0HZA5F | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Tape and Reel |
| NAND32GAH0PZA5E | 制造商:Micron Technology Inc 功能描述:EMMC 4.3 4GB 12X16 41NM - Trays |
| NAND32GAH0PZA5F | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Tape and Reel |
| NAND32GAHAKZO6E | 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE - Trays |
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