參數(shù)資料
型號(hào)： NAND256W4A2AZA6E
廠商： NUMONYX
元件分類： PROM
英文描述： 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55
封裝： 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55
文件頁(yè)數(shù)： 21/58頁(yè)
文件大?。?/td> 1406K
代理商： NAND256W4A2AZA6E
Device operations
NAND128-A, NAND256-A
6.5
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
An erase operation consists of the following three steps (refer to Figure 16: Block erase
1.
One bus cycle is required to set up the Block Erase command.
2.
Only two bus cycles are required to input the block address. The first cycle (A0 to A7) is
not required as only addresses A14 to A26 (highest address depends on device
density) are valid, A9 to A13 are ignored. In the last address cycle I/O2 to I/O7 must be
set to VIL.
3.
One bus cycle is required to issue the confirm command to start the P/E/R controller.
Once the erase operation has completed the status register can be checked for errors.
Figure 16.
Block erase operation
6.6
Reset
The Reset command resets the command interface and status register. If the Reset
command is issued during any operation, the operation is aborted. If it was a program or
erase operation that was aborted, the contents of the memory locations being modified are
no longer valid as the data is partially programmed or erased.
If the device has already been reset then the new Reset command is not accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the operation that the device was performing when the command was
issued (refer to Table 20: AC characteristics for operations for the values.)
6.7
Read status register
The device contains a status register which provides information on the current or previous
program or erase operation. the various bits in the status register convey information and
errors on the operation.
the status register is read by issuing the read status register command. the status register
information is present on the output data bus (I/O0-I/O7) on the falling edge of chip enable
or read enable, whichever occurs last. when several memories are connected in a system,
the use of chip enable and read enable signals allows the system to poll each device
separately, even when the ready/busy pins are common-wired. it is not necessary to toggle
the chip enable or read enable signals to update the contents of the status register.
I/O
RB
Block Address
Inputs
SR0
ai07593
D0h
70h
60h
Block Erase
Setup Code
Confirm
Code
Read Status Register
Busy
tBLBH3
(Erase Busy time)
相關(guān)PDF資料
PDF描述
NCP303LSN41T1 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO5
NCS6416DWG 8-CHANNEL, VIDEO MULTIPLEXER, PDSO20
NCS6S4803L5C 1-OUTPUT 5 W DC-DC REG PWR SUPPLY MODULE
NCT050C-20.0000 CRYSTAL OSCILLATOR, CLOCK, 20 MHz, TTL OUTPUT
NCT250A-FREQ-OUT3 CRYSTAL OSCILLATOR, CLOCK, 4 MHz - 20 MHz, TTL OUTPUT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NAND32GAH0HZA5E 制造商:Micron Technology Inc 功能描述:NAND EMMC - Trays
NAND32GAH0HZA5F 制造商:Micron Technology Inc 功能描述:NAND EMMC - Tape and Reel
NAND32GAH0PZA5E 制造商:Micron Technology Inc 功能描述:EMMC 4.3 4GB 12X16 41NM - Trays
NAND32GAH0PZA5F 制造商:Micron Technology Inc 功能描述:NAND EMMC - Tape and Reel
NAND32GAHAKZO6E 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE - Trays
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*