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參數(shù)資料
| 型號(hào)： | NAND256W4A2AZA6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55 |
| 文件頁數(shù)： | 22/58頁 |
| 文件大?。?/td> | 1406K |
| 代理商： | NAND256W4A2AZA6E |
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NAND128-A, NAND256-A
Device operations
29/58
After the read status register command has been issued, the device remains in read status
register mode until another command is issued. therefore if a read status register command
is issued during a random read cycle a new read command must be issued to continue with
a page read.
The status register bits are summarized in Table 11: Status register bits, to which you should
refer in conjunction with the following sections.
6.7.1
Write protection bit (SR7)
The write protection bit identifies if the device is protected or not. If the write protection bit is
set to ‘1’ the device is not protected and program or erase operations are allowed. If the
write protection bit is set to ‘0’ the device is protected and program or erase operations are
not allowed.
6.7.2
P/E/R controller bit (SR6)
The program/erase/read controller bit indicates whether the P/E/R controller is active or
inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
6.7.3
Error bit (SR0)
The error bit identifies if any errors have been detected by the P/E/R controller. The error bit
is set to ’1’ when a program or erase operation has failed to write the correct data to the
memory. If the error bit is set to ‘0’ the operation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are reserved.
6.8
Read electronic signature
The device contains a manufacturer code and device code. To read these codes the following
two steps are required:
1.
First use one bus write cycle to issue the Read Electronic Signature command (90h),
followed by an address input of 00h.
2.
Then, perform two bus read operations. The first one reads the manufacturer code and
the second reads the device code. Further bus read operations are ignored.
Table 11.
Status register bits
Bit
Name
Logic level
Definition
SR7
Write protection
'1'
Not protected
'0'
Protected
SR6
Program/erase/read
controller
'1'
P/E/R C inactive, device ready
'0'
P/E/R C active, device busy
SR5, SR4, SR3,
SR2, SR1
Reserved
’don’t care’
SR0
Generic error
‘1’
Error – operation failed
‘0’
No error – operation successful
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| NAND32GAH0HZA5E | 制造商:Micron Technology Inc 功能描述:NAND EMMC - Trays |
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