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參數資料
| 型號： | NAND256W4A2AZA6E |
| 廠商： | NUMONYX |
| 元件分類： | PROM |
| 英文描述： | 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55 |
| 封裝： | 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55 |
| 文件頁數： | 55/58頁 |
| 文件大小： | 1406K |
| 代理商： | NAND256W4A2AZA6E |
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Description
NAND128-A, NAND256-A
1
Description
The NAND flash 528-byte/ 264-word page is a family of non-volatile flash memories that
uses the single level cell (SLC) NAND cell technology, referred to as the SLC small page
family. The devices are either 128 Mbits or 256 Mbits and operate with 3 V voltage supply.
The size of a page is either 528 bytes (512 + 16 spare) or 264 words (256 + 8 spare)
depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the data input/output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
Each block can be programmed and erased up to 100,000 cycles. To extend the lifetime of
NAND flash devices it is strongly recommended to implement an error correction code
(ECC). A Write Protect pin is available to provide hardware protection against program and
erase operations.
The devices feature an open-drain ready/busy output that identifies if the program/erase/
read (P/E/R) controller is currently active. The use of an open-drain output allows the
Ready/Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When
a page program operation fails, the data can be programmed in another page without having
to resend the data to be programmed.
Table 1 lists the individual part numbers of the device.
The devices are available in the following packages:
●
TSOP48 12 x 20 mm for all products
●
VFBGA55 (8 x 10 x 1 mm, 6 x 8 ball array, 0.8 mm pitch)
and in two different versions:
●
No option (Chip Enable ‘care’, sequential row read enabled): the sequential row read
feature allows to download up to all the pages in a block with one read command and
addressing only the first page to read
●
With Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between
more active memories that are simultaneously active as Chip Enable transitions during
latency do not stop read operations. Program and erase operations are not interrupted
by Chip Enable transitions.
A serial number (unique identifier) option enables each device to be uniquely identified. The
serial number options is subject to an NDA (non-disclosure agreement) and is not described
in this datasheet. For more details of this option contact your nearest Numonyx sales office.
Table 1.
NAND128-A and NAND256-A device summary
Reference
Part Number
NAND128-A
NAND128W3A
NAND256-A(1)
1.
x16 organization only available for MCP.
NAND256W3A
NAND256W4A
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