參數(shù)資料
型號: NAND256W4A2AZA6E
廠商: NUMONYX
元件分類: PROM
英文描述: 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55
封裝: 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55
文件頁數(shù): 28/58頁
文件大?。?/td> 1406K
代理商: NAND256W4A2AZA6E
Software algorithms
NAND128-A, NAND256-A
7.5
Error correction code
An error correction code (ECC) can be implemented in the NAND flash memories to identify
and correct errors in the data.
The recommendation is to implement 23 bits of ECC for every 4096 bits in the device.
Figure 19.
Error detection
7.6
Hardware simulation models
7.6.1
Behavioral simulation models
Denali Software Corporation models are platform-independent functional models designed
to assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND flash devices, and, therefore, allow
software to be developed before hardware.
7.6.2
IBIS simulations models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of flash devices.
These models provide information such as AC characteristics, rise/fall times, and package
mechanical data, all of which are measured or simulated at voltage and temperature ranges
wider than those allowed by target specifications.
IBIS models simulate PCB connections and can resolve compatibility issues when
upgrading devices. They can be imported into SPICETOOLS.
New ECC generated
during read
XOR previous ECC
with new ECC
All results
= zero?
22 bit data = 0
YES
11 bit data = 1
NO
1 bit data = 1
Correctable
Error
ECC Error
No Error
ai08332
>1 bit
= zero?
YES
NO
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