參數(shù)資料
型號: NAND256W4A2AZA6E
廠商: NUMONYX
元件分類: PROM
英文描述: 16M X 16 FLASH 3V PROM, 12000 ns, PBGA55
封裝: 8 X 10 MM, 1 MM HEIGHT, 0.80 MM PITCH, ROHS COMPLIANT, VFBGA-55
文件頁數(shù): 10/58頁
文件大小: 1406K
代理商: NAND256W4A2AZA6E
Bus operations
NAND128-A, NAND256-A
4
Bus operations
There are six standard bus operations that control the memory. Each of these is described
in this section, see Table 5: Bus operations for a summary.
4.1
Command input
Command input bus operations give commands to the memory. Commands are accepted
when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable is Low,
and Read Enable is High. They are latched on the rising edge of the Write Enable signal.
Only I/O0 to I/O7 input commands.
program erase endurance cycles for details of the timings requirements.
4.2
Address input
Address input bus operations input the memory address. Three bus cycles are required to
input the addresses (refer to Tables Table 6: Address insertion, x8 devices and Table 7:
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low, and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 input addresses.
program erase endurance cycles for details of the timings requirements.
4.3
Data input
Data input bus operations input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal and is input sequentially using the Write Enable signal.
of the timings requirements.
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