參數資料
型號: NAND128W3A2BV6E
廠商: STMICROELECTRONICS
元件分類: PROM
英文描述: 16M X 8 FLASH 3V PROM, 12000 ns, PDSO48
封裝: 12 X 17 MM, 0.65 MM HEIGHT, ROHS COMPLIANT, PLASTIC, USOP-48
文件頁數: 54/56頁
文件大?。?/td> 951K
代理商: NAND128W3A2BV6E
7/56
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
SUMMARY DESCRIPTION
The NAND Flash 528 Byte/ 264 Word Page is a
family of non-volatile Flash memories that uses
the Single Level Cell (SLC) NAND cell technology.
It is referred to as the Small Page family. The de-
vices range from 128Mbits to 1Gbit and operate
with either a 1.8V or 3V voltage supply. The size of
a Page is either 528 Bytes (512 + 16 spare) or 264
Words (256 + 8 spare) depending on whether the
device has a x8 or x16 bus width.
The address lines are multiplexed with the Data In-
put/Output signals on a multiplexed x8 or x16 In-
put/Output bus. This interface reduces the pin
count and makes it possible to migrate to other
densities without changing the footprint.
Each block can be programmed and erased over
100,000 cycles. To extend the lifetime of NAND
Flash devices it is strongly recommended to imple-
ment an Error Correction Code (ECC). A Write
Protect pin is available to give a hardware protec-
tion against program and erase operations.
The devices feature an open-drain Ready/Busy
output that can be used to identify if the Program/
Erase/Read (P/E/R) Controller is currently active.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor.
A Copy Back command is available to optimize the
management of defective blocks. When a Page
Program operation fails, the data can be pro-
grammed in another page without having to re-
send the data to be programmed.
The devices are available in the following packag-
es:
TSOP48 12 x 20mm for all products
USOP48 12 x 17 x 0.65mm for 128Mb, 256Mb
and 512Mb products
VFBGA55 (8 x 10 x 1mm, 6 x 8 ball array,
0.8mm pitch) for 128Mb and 256Mb products
VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array,
0.8mm pitch) for the 512Mb product
All devices have the Chip Enable Don't Care op-
tion, which allows the code to be directly down-
loaded by a microcontroller, as Chip Enable
transitions during the latency time do not stop the
read operation.
A Serial Number option, allows each device to be
uniquely identified. The Serial Number options is
subject to an NDA (Non Disclosure Agreement)
and so not described in the datasheet. For more
details of this option contact your nearest ST Sales
office.
For information on how to order these options refer
vices are shipped from the factory with Block 0 al-
ways valid and the memory content bits, in valid
blocks, erased to ’1’.
See Table 2., Product Description, for all the de-
相關PDF資料
PDF描述
NAND512R3A2CV6E 64M X 8 FLASH 1.8V PROM, 15000 ns, PDSO48
NAND128W4A2CZA6E 8M X 16 FLASH 3V PROM, 35 ns, PBGA55
NAND128R4A2BZA6E 8M X 16 FLASH 1.8V PROM, 35 ns, PBGA55
NAND256R4A0DN6T 16M X 16 FLASH 1.8V PROM, 15000 ns, PDSO48
NAND256R4A2DZA1F 16M X 16 FLASH 1.8V PROM, 15000 ns, PBGA63
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