參數(shù)資料
型號: MT55V1MV18P
廠商: Micron Technology, Inc.
英文描述: 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器)
中文描述: 16Mb的:1梅格× 18,流量通過ZBT SRAM的(16Mb的流通式同步靜態(tài)存儲器)
文件頁數(shù): 6/34頁
文件大?。?/td> 460K
代理商: MT55V1MV18P
6
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS
x18
37
36
x32/36
37
36
32-35, 44-50,
81-84, 99, 100
SYMBOL
SA0
SA1
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and
must meet the setup and hold times around the rising edge
of CLK. SA0 and SA1 are the two least significant bits (LSB)
of the address field and set the internal burst counter if burst
is desired.
Synchronous Byte Write Enables: These active LOW inputs
allow individual bytes to be written when a WRITE cycle is
active and must meet the setup and hold times around the
rising edge of CLK. BYTE WRITEs need to be asserted on the
same cycle as the address. BWs are associated with addresses
and apply to subsequent data. BWa# controls DQa pins; BWb#
controls DQb pins; BWc# controls DQc pins; BWd# controls
DQd pins.
Clock: This signal registers the address, data, chip enables, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around
the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD# LOW).
Synchronous Chip Enable: This active LOW input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to
enable the device and is sampled only when a new external
address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
Output Enable: This
active LOW, asynchronous input enables
the data I/O output drivers. G# is the JEDEC-standard term for
OE#.
Synchronous Address Advance/Load: When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new
address at the CLK rising edge.
Synchronous Clock Enable: This active LOW input permits CLK
to propagate throughout the device. When CKE# is HIGH, the
device ignores the CLK input and effectively internally extends
the previous CLK cycle. This input must meet setup and hold
times around the rising edge of CLK.
Snooze Enable: This active HIGH, asynchronous input causes
the device to enter a low-power standby mode in which all
data in the memory array is retained. When ZZ is active, all
other inputs are ignored.
This pin has an internal pull-down
and can be floating.
32-35, 44-50,
80-84, 99, 100
93
94
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
97
97
CE2
Input
86
86
OE#
(G#)
Input
85
85
ADV/LD#
Input
87
87
CKE#
Input
64
64
ZZ
Input
(continued on next page)
相關(guān)PDF資料
PDF描述
MT55L512L18F 8Mb: 512K x 18,Flow-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器)
MT55L256L32F 8Mb: 256K x 32,F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器)
MT55L256L36F 8Mb: 256K x 36,F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器)
MT55L256V32F 8Mb: 256K x 32,F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器)
MT55L256V36F 8Mb: 256K x 36,F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器)
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