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參數(shù)資料
| 型號(hào)： | MT55L256V36F |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 8Mb: 256K x 36，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器) |
| 中文描述： | 8MB的：256K × 36，流量通過ZBT SRAM的（8兆流通式同步靜態(tài)存儲(chǔ)器） |
| 文件頁數(shù)： | 1/25頁 |
| 文件大?。?/td> | 380K |
| 代理商： | MT55L256V36F |
1
8Mb: 512K x 18, 256K x 32/36 Flow-Through ZBT SRAM
MT55L512L18F_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
8Mb: 512K x 18, 256K x 32/36
FLOW-THROUGH ZBT SRAM
NOTE:
1. JEDEC-standard MS-026 BHA (LQFP).
8Mb
ZBT
SRAM
FEATURES
High frequency and 100 percent bus utilization
Fast cycle times: 10ns, 11ns and 12ns
100-pin TQFP
165-pin FBGA
Single +3.3V ±5% power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
Advanced control logic for minimum control
signal interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or Interleaved Burst Modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 4Mb, and
16Mb ZBT SRAM
Automatic power-down
OPTIONS
Timing (Access/Cycle/MHz)
7.5ns/10ns/100 MHz
8.5ns/11ns/90 MHz
9ns/12ns/83 MHz
Configurations
3.3V I/O
512K x 18
256K x 32
256K x 36
2.5V I/O
512K x 18
256K x 32
256K x 36
Package
100-pin TQFP
165-pin FBGA
MARKING*
-10
-11
-12
MT55L512L18F
MT55L256L32F
MT55L256L36F
MT55L512V18F
MT55L256V32F
MT55L256V36F
T
F
Part Number Example:
MT55L256L32FT-11
*A Part Marking Guide for the FBGA devices can be found on Micron’s
web site—
http://www.micronsemi.com/support/index.html
.
MT55L512L18F, MT55L512V18F,
MT55L256L32F, MT55L256V32F,
MT55L256L36F, MT55L256V36F
3.3V V
DD
, 3.3V or 2.5V I/O
100-Pin TQFP
1
165-Pin FBGA
(Preliminary Package Data)
GENERAL DESCRIPTION
The Micron
Zero Bus Turnaround
(ZBT
) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 8Mb ZBT SRAMs integrate a 512K x 18,
256K x 32, or 256K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55L256V36FF-10ES | 制造商:Cypress Semiconductor 功能描述: |
| MT55L256V36P | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:8Mb ZBT SRAM |
| MT55L256V36PF7.5 | 制造商:MICRO CHIP 功能描述: |
| MT55L256V36PT10 | 制造商:Micron Technology Inc 功能描述: |
| MT55L256V36PT-6 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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