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參數(shù)資料
| 型號： | MT55V1MV18P |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲器) |
| 中文描述： | 16Mb的：1梅格× 18，流量通過ZBT SRAM的（16Mb的流通式同步靜態(tài)存儲器） |
| 文件頁數(shù)： | 2/34頁 |
| 文件大?。?/td> | 460K |
| 代理商： | MT55V1MV18P |
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16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The data associated with the address is
required two cycles later, or on the rising edge of clock
cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa#
controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; and BWd# controls DQd pins. Cycle
types can only be defined when an address is loaded,
i.e., when ADV/LD# is LOW. Parity/ECC bits are only
available on the x36 versions.
Micron’s 16Mb ZBT SRAMs operate from a +3.3V or
+2.5V V
DD
power supply, and all 3.3V V
DD
inputs and
outputs are LVTTL-compatible. Users can implement
either a 3.3V or 2.5V I/O for the +3.3V V
DD
or a 2.5V
I/O for the +2.5V V
DD
. The device is ideally suited for
systems requiring high bandwidth and zero bus turn-
around delays.
refer the www.micronsemi.com/en/products/sram/inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc# and BWd#) and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin (MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The data-out (Q),
enabled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.
All READ, WRITE, and DESELECT cycles are initi-
ated by the ADV/LD# input. Subsequent burst ad-
dresses can be internally generated as controlled by the
burst advance pin (ADV/LD#). Use of burst mode is
optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
GENERAL DESCRIPTION (continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT55L512L18F | 8Mb: 512K x 18,Flow-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| MT55L256L32F | 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| MT55L256L36F | 8Mb: 256K x 36，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| MT55L256V32F | 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
| MT55L256V36F | 8Mb: 256K x 36，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲器) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT55V1MV18PT-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
| MT55V512V32FT-8.8 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55V512V32PF-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT55V512V32PF-6 | 制造商:Rochester Electronics LLC 功能描述: |
| MT55V512V32PT-10 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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