參數(shù)資料
型號(hào)： MT55V1MV18P
廠商： Micron Technology, Inc.
英文描述： 16Mb: 1 Meg x 18, Flow-Through ZBT SRAM(16Mb流通式同步靜態(tài)存儲(chǔ)器)
中文描述： 16Mb的：1梅格× 18，流量通過(guò)ZBT SRAM的（16Mb的流通式同步靜態(tài)存儲(chǔ)器）
文件頁(yè)數(shù)： 24/34頁(yè)
文件大?。?/td> 460K
代理商： MT55V1MV18P
24
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1M18P_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)
The 16Mb SRAM incorporates a serial boundary
scan test access port (TAP). This port operates in accor-
dance with IEEE Standard 1149.1-1990 but does not
have the set of functions required for full 1149.1 com-
pliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay
in the critical speed path of the SRAM. Note that the
TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register and ID
register.
DISABLING THE JTAG FEATURE
These pins can be left floating (unconnected), if the
JTAG function is not to be implemented. Upon power-
up, the device will come up in a reset state which will
not interfere with the operation of the device.
TEST ACCESS PORT (TAP)
TEST CLOCK (TCK)
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this pin unconnected if the TAP is
not used. The pin is pulled up internally, resulting in a
logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 5. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register. (See Figure 6.)
Figure 5
TAP Controller State Diagram
NOTE:
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
相關(guān)PDF資料
PDF描述
MT55L512L18F 8Mb: 512K x 18,Flow-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
MT55L256L32F 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
MT55L256L36F 8Mb: 256K x 36，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
MT55L256V32F 8Mb: 256K x 32，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
MT55L256V36F 8Mb: 256K x 36，F(xiàn)low-Through ZBT SRAM(8Mb流通式同步靜態(tài)存儲(chǔ)器)
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