參數(shù)資料
型號(hào): MT54V512H18A
廠商: Micron Technology, Inc.
英文描述: 512K x 18 Synchronous Pipelined Burst SRAM(9Mb,流水線式,同步脈沖靜態(tài)存儲(chǔ)器)
中文描述: 為512k × 18同步流水線突發(fā)靜態(tài)存儲(chǔ)器(9Mb以上,流水線式,同步脈沖靜態(tài)存儲(chǔ)器)
文件頁(yè)數(shù): 8/22頁(yè)
文件大?。?/td> 258K
代理商: MT54V512H18A
8
512K x 18 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V512H18A.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb2 SRAM
BUS CYCLE STATE DIAGRAM
LOAD NEW
READ ADDRESS
READ DOUBLE
POWER-UP
Supply voltage
provided
READ PORT NOP
R_Init=0
RD
RD
always
/RD
/RD
LOAD NEW
WRITE ADDRESS
AT K#
WRITE DOUBLE
AT K#
Supply voltage
provided
WRITE PORT NOP
WT
WT
always
/WT
/WT
NOTE:
1. The address is concatenated with 1 additional internal LSB to facilitate burst operation. The address order is always
fixed as: xxx...xxx+0, xxx...xxx+1. Bus cycle is terminated at the end of this sequence (burst count = 2).
2. State transitions: RD = (R# = LOW); WT = (W# = LOW).
3. Read and write state machines can be active simultaneously.
4. State machine control timing sequence is controlled by K.
相關(guān)PDF資料
PDF描述
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