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參數(shù)資料
| 型號： | MT54V512H18A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 為512k × 18同步流水線突發(fā)靜態(tài)存儲器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 258K |
| 代理商： | MT54V512H18A |
5
512K x 18 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V512H18A.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb2 SRAM
PIN DESCRIPTIONS
PINS (x18)
6C
7C
4B, 8B,
5C, 5N-7N,
4P, 5P, 7P,
8P, 3R-5R,
7R-9R
8A
SYMBOL
SA
TYPE
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered and must meet
the setup and hold times around the rising edge of K for READ cycles and
must meet the setup and hold times around the rising edge of K# for
WRITE cycles. Pins 9A, 3A, 10A, and 2A are reserved for the next higher
-order address inputs on 18, 36, 72, and 144Mb devices, respectively. All
transactions operate on a burst of two 18-bit data (one clock period of
bus activity). These inputs are ignored when both ports are deselected.
Synchronous Read: When LOW this input causes the address inputs to be
registered and a READ cycle to be initiated. This input must meet setup
and hold times around the rising edge of K.
Synchronous Write: When LOW this input causes the address inputs to be
registered and a WRITE cycle to be initiated. This input must meet setup
and hold times around the rising edge of K.
Synchronous Byte Writes: When LOW these inputs cause their respective
byte to be registered and written if W# had initiated a WRITE cycle. BW0#
and BW1# must meet setup and hold times around the rising edges of K
and K# for each of the two rising edges comprising the WRITE cycle.
BW0# controls D0-D8. BW1# controls D9-D17.
Input Clock: This input clock pair registers address and
control inputs on the rising edge of K, and registers data on the rising
edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times
around the clock rising edges.
Output Clock: This clock pair provides a user controlled means of
tuning device output data. The rising edge of C is used as the output
timing reference for first output data. The rising edge of C# is used as the
output reference for second output data. Ideally, C# is 180 degrees out of
phase with C. C and C# may be tied HIGH to force the use of K and K# as
the output reference clocks instead of having to provide C and C# clocks.
If tied HIGH, these inputs may not be allowed to toggle during device
operation.
IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These pins may be
left Not Connected if the JTAG function is not used in the circuit.
IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This pin must be
tied to V
SS
if the JTAG function is not used in the circuit.
HSTL Input Reference Voltage: Nominally V
DD
Q/2 but may be adjusted to
improve system noise margin. Provides a reference voltage for the HSTL
input buffer trip point.
Output Impedance Matching Input: This input is used to tune the device
outputs to the system data bus impedance. DQ output impedance is set to
0.2 x RQ, where RQ is a resistor from this pin to ground. Alternately, this
pin can be connected directly to V
DD
, which enables the minimum
impedance mode. This pin cannot be connected directly to GND or left
unconnected.
R#
Input
4A
W#
Input
7B
5A
BW0#
BW1#
Input
6B
6A
K
K#
Input
6P
6R
C
C#
Input
10R
11R
2R
TMS
TDI
TCK
Input
Input
2H, 10H
V
REF
Input
11H
ZQ
Input
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相關代理商/技術參數(shù) |
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