參數(shù)資料
型號(hào): MT54V512H18A
廠商: Micron Technology, Inc.
英文描述: 512K x 18 Synchronous Pipelined Burst SRAM(9Mb,流水線式,同步脈沖靜態(tài)存儲(chǔ)器)
中文描述: 為512k × 18同步流水線突發(fā)靜態(tài)存儲(chǔ)器(9Mb以上,流水線式,同步脈沖靜態(tài)存儲(chǔ)器)
文件頁(yè)數(shù): 6/22頁(yè)
文件大?。?/td> 258K
代理商: MT54V512H18A
6
512K x 18 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V512H18A.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb2 SRAM
10P
11N
11M
10K
11J
11G
10E
11D
11C
3B
3C
2D
3F
2G
3J
3L
3M
2N
1A, 11A
1R
11P
10M
11L
11K
10J
11F
11E
10C
11B
2B
3D
3E
2F
3G
3K
2L
3N
3P
5F, 7F, 5G,
7G, 5H, 7H,
5J,7J, 5K,
7K
4E, 8E, 4F,
8F, 4G, 8G,
3H, 4H, 8H,
9H, 4J, 8J,
4K, 8K, 4L,
8L
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
DNU
TDO
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
V
DD
Input
Synchronous Data Inputs: Input data must meet setup and hold times
around the rising edges of K and K# during WRITE operations.
Output
Output
Output
Do Not Use. These pins should not be used.
IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level.
Synchronous Data Outputs: Output data is synchronized to the
respective C and C# or to K and K# rising edges if C and C# are tied
HIGH. This bus operates in response to R# commands.
Supply
Power Supply: 2.5V nominal. See DC Electrical Characteristics and
Operating Conditions for range.
V
DD
Q
Supply
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. See DC
Electrical Characteristics and Operating Conditions for range.
PIN DESCRIPTIONS (continued)
PINS (x18)
SYMBOL
TYPE
DESCRIPTION
相關(guān)PDF資料
PDF描述
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