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參數(shù)資料
| 型號： | MT54V512H18A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 512K x 18 Synchronous Pipelined Burst SRAM(9Mb，流水線式，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 為512k × 18同步流水線突發(fā)靜態(tài)存儲器（9Mb以上，流水線式，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 15/22頁 |
| 文件大小： | 258K |
| 代理商： | MT54V512H18A |
15
512K x 18 2.5V V
DD
, HSTL, QDRb2 SRAM
MT54V512H18A.p65 – Rev. 3/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
512K x 18
2.5V V
DD
, HSTL, QDRb2 SRAM
IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)
The QDR SRAM incorporates a serial boundary scan
test access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are ex-
cluded because their inclusion places an added delay in
the critical speed path of the SRAM. Note that the TAP
controller functions in a manner that does not conflict
with the operation of other devices using 1149.1 fully
compliant TAPs. The TAP operates using JEDEC-stan-
dard 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and ID
register.
DISABLING THE JTAG FEATURE
It is possible to operate the SRAM without using the
JTAG feature. To disable the TAP controller, TCK must
be tied LOW (V
SS
) to prevent clocking of the device. TDI
and TMS are internally pulled up and may be uncon-
nected. They may alternately be connected to V
DD
through a pull-up resistor. TDO should be left uncon-
nected. Upon power-up, the device will come up in a
reset state which will not interfere with the operation
of the device.
TEST ACCESS PORT (TAP)
TEST CLOCK (TCK)
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this pin unconnected if the TAP is
not used. The pin is pulled up internally, resulting in a
logic HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 2. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register. (See Figure 3.)
Figure 2
TAP Controller State Diagram
NOTE:
The 0/1 next to each state represents the value of
TMS at the rising edge of TCK.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
Bypass Register
0
Instruction Register
0
1
2
Identification Register
0
1
2
29
30
31
.
.
.
Boundary Scan Register
0
1
2
.
.
x
.
.
.
Selection
Circuitry
Selection
Circuitry
TCK
TMS
TAP CONTROLLER
TDI
TDO
x = 69 for the x18 configuration.
Figure 3
TAP Controller Block Diagram
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