參數(shù)資料
型號： MT48LC4M32B2
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁數(shù)： 49/52頁
文件大?。?/td> 1281K
代理商： MT48LC4M32B2
49
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
SDRAM
ALTERNATING BANK WRITE ACCESSES
1
DON’T CARE
tCH
tCL
tCK
CLK
DQ
D
IN
m
tDH
tDS
D
IN
m
+ 1
D
IN
m
+ 2
D
IN
m
+ 3
COMMAND
tCMH
NOP
NOP
tCMS
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
tDH
tDS
tDH
tDS
tDH
tDS
ACTIVE
WRITE
D
IN
b
tDH
tDS
D
IN
b
+ 1
D
IN
b
+ 3
tDH
tDS
tDH
tDS
ENABLE AUTO PRECHARGE
A10
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
ROW
ROW
ROW
ENABLE AUTO PRECHARGE
ROW
ROW
BANK 0
BANK 0
BANK 1
CKE
tCKH
tCKS
D
IN
b
+ 2
tDH
tDS
COLUMN b
3
COLUMN
m
3
tRP - BANK 0
tRAS - BANK 0
t
RC - BANK 0
tRCD - BANK 0
t
t
RCD - BANK 0
tWR
2
- BANK 0
WR - BANK 4
tRCD - BANK 4
t
RRD
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
BA0, BA1
DQM 0-3
A0-A9, A11
BANK 0
BANK 1
NOTE:
1. For this example, the burst length = 4.
2. Faster frequencies require two clocks (when
t
WR >
t
CK).
3. A8, A9, and A11 = “Don’t Care.”
*CAS latency indicated in parentheses.
-6
-7
SYMBOL*
t
DH
t
DS
t
RAS
t
RC
t
RCD
t
RP
t
RRD
t
WR
t
WR
MIN
1
1.5
42
60
18
18
14
2
1 CLK+
6
MAX
MIN
1
2
42
70
20
20
14
2
1 CLK+
7
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
120,000
120,000
ns
TIMING PARAMETERS
-6
-7
SYMBOL*
t
AH
t
AS
t
CH
t
CL
t
CK (3)
t
CK (2)
t
CK (1)
t
CKH
t
CKS
t
CMH
t
CMS
MIN
1
1.5
2.5
2.5
6
10
20
1
2
1
1.5
MAX
MIN
1
2
2.75
2.75
7
10
20
1
2
1
2
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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