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參數(shù)資料
| 型號： | MT48LC4M32B2 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | SYNCHRONOUS DRAM |
| 中文描述： | 同步DRAM |
| 文件頁數(shù)： | 26/52頁 |
| 文件大?。?/td> | 1281K |
| 代理商： | MT48LC4M32B2 |
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26
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
SDRAM
TRUTH TABLE 2 – CKE
(Notes: 1-4)
CKE
n-1
CKE
n
L
CURRENT STATE
Power-Down
Self Refresh
Clock Suspend
Power-Down
Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
Reading or Writing
COMMAND
n
X
X
X
ACTION
n
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Exit Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
NOTES
L
L
H
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
AUTO REFRESH
VALID
See Truth Table 3
5
6
7
H
L
H
H
NOTE:
1. CKE
n
is the logic state of CKE at clock edge
n
; CKE
n-1
was the state of CKE at the previous clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge
n
.
3. COMMAND
n
is the command registered at clock edge
n
, and ACTION
n
is a result of COMMAND
n
.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge
n
will put the device in the all banks idle state in time for clock
edge
n + 1
(provided that
t
CKS is met).
6. Exiting self refresh at clock edge
n
will put the device in the all banks idle state once
t
XSR is met.
COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the
t
XSR
period. A minimum of two NOP commands must be provided during
t
XSR period.
7. After exiting clock suspend at clock edge
n
, the device will resume operation and recognize the next
command at clock edge
n + 1
.
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