
7
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
NOTE:
1. Two devices may not drive the memory bus at the same time.
2. Allowable Flash read modes include read array, read query, read configuration, and read status.
3. Outputs are dependent on a separate device controlling bus outputs.
4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.
5. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.
6. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to
control the bus outputs at a time.
7. Data output on lower byte only; upper byte High-Z.
8. Data output on upper byte only; lower byte High-Z.
9. Data input on lower byte only.
10. Data input on upper byte only.
TRUTH TABLE – FLASH
FLASH SIGNALS
F_CE#
SRAM SIGNALS
MEMORY OUPUT
MEMORY
BUS CONTROL
Flash
Flash
Other
Other
Other
MODES
F_RP#
F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#
DQ0–DQ15
NOTES
Read
Write
Standby
Output Disable
Reset
H
H
H
H
L
L
L
H
L
X
L
H
X
H
X
H
L
X
H
X
SRAM must be High-Z
D
OUT
D
IN
High-Z
High-Z
High-Z
1, 2, 3
1
4
4, 5
4, 6
SRAM any mode allowable
TRUTH TABLE – SRAM
FLASH SIGNALS
F_CE#
SRAM SIGNALS
MEMORY OUPUT
MEMORY
BUS CONTROL
MODES
F_RP#
F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#
DQ0–DQ15
NOTES
Read
DQ0–DQ15
DQ0–DQ7
DQ8–DQ15
Write
DQ0–DQ15
DQ0–DQ7
DQ8–DQ15
Standby
L
L
L
H
H
H
L
L
L
H
H
H
L
H
L
L
L
H
SRAM
SRAM
SRAM
D
OUT
D
OUT
LB
D
OUT
UB
1, 3
7
8
Flash must be High-Z
L
L
L
H
X
L
H
H
H
X
L
H
H
H
H
X
X
X
L
L
L
X
X
X
L
H
L
X
X
X
L
L
H
X
X
X
SRAM
SRAM
SRAM
Other
Other
Other
D
IN
D
IN
LB
D
IN
UB
High-Z
High-Z
High-Z
1, 3
9
10
4
4
4
Flash any mode allowable
Output Disable