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參數(shù)資料
| 型號： | MT28C3224P20 |
| 廠商： | Micron Technology, Inc. |
| 元件分類： | DRAM |
| 英文描述： | FLASH AND SRAM COMBO MEMORY |
| 中文描述： | 閃存和SRAM式內(nèi)存 |
| 文件頁數(shù)： | 5/42頁 |
| 文件大?。?/td> | 498K |
| 代理商： | MT28C3224P20 |
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5
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
BALL DESCRIPTIONS
66-BALL FBGA
NUMBERS
H6, G9, G8, G7,
H5, H4, G6, G5,
B4, B6, B5, A4,
A8, A7, A6, A5,
B3, G4, G3, E5,
A3
H7
SYMBOL
A0–A20
TYPE
Input
DESCRIPTION
Address Inputs: Inputs for the addresses during READ and WRITE
operations. Addresses are internally latched during READ and WRITE
cycles. Flash: A0–A20; SRAM: A0–A17.
F_CE#
Input
Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.
Flash Output Enable: Enables Flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.
Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.
Reset. When F_RP# is a logic LOW, the device is in reset, which drives
the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,
the device is in standard operation. When F_RP# transitions from logic
LOW to logic HIGH, the device resets all blocks to locked and defaults to
the read array mode.
Flash Write Protect. Controls the lock down function of the flexible
locking feature.
SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.
SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.
SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.
SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0–DQ7).
SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8–DQ15).
Data Inputs/Outputs: Input array data on the second CE# and WE#
cycle during PROGRAM command. Input commands to the command
user interface when CE# and WE# are active. Output data when CE#
and OE# are active.
H9
F_OE#
Input
C3
F_WE#
Input
D4
F_RP#
Input
E3
F_WP#
Input
G10
S_CE1#
Input
D8
S_CE2
Input
F5
S_OE#
Input
B8
S_WE#
Input
F3
S_LB#
Input
F4
S_UB#
Input
F9, F10, E9,
E10, C9, C10,
C8, B10, F8,
F7, E8, E6, D7,
C7, B9, B7
DQ0–DQ15
Input/
Output
(continued on next page)
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相關(guān)代理商/技術(shù)參數(shù) |
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| MT28C3224P20FL-80 BET | 制造商:Micron Technology Inc 功能描述: |
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