參數(shù)資料
型號(hào)： MT28C3224P20
廠商： Micron Technology, Inc.
元件分類(lèi)： DRAM
英文描述： FLASH AND SRAM COMBO MEMORY
中文描述： 閃存和SRAM式內(nèi)存
文件頁(yè)數(shù)： 23/42頁(yè)
文件大小： 498K
代理商： MT28C3224P20
F
23
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
protection configuration register, the READ ARRAY
command, FFh, must be issued to the bank containing
address 00h prior to issuing other commands.
LOCKING OPERATIONS DURING ERASE
SUSPEND
Changes to block lock status can be performed dur-
ing an ERASE SUSPEND by using the standard locking
command sequences to unlock, lock, or lock down. This
is useful in the case when another block needs to be
updated while an ERASE operation is in progress.
To change block locking during an ERASE opera-
tion, first write the ERASE SUSPEND command (B0h),
then check the status register until it indicates that the
ERASE operation has been suspended. Next, write the
desired lock command sequence to block lock, and the
lock status will be changed. After completing any de-
sired LOCK, READ, or PROGRAM operations, resume
the ERASE operation with the ERASE RESUME com-
mand (D0h).
If a block is locked or locked down during an ERASE
SUSPEND on the same block, the locking status bits
are changed immediately. When the ERASE is resumed,
the ERASE operation completes.
A locking operation cannot be performed during a
PROGRAM SUSPEND.
STATUS REGISTER ERROR CHECKING
Using nested locking or program command se-
quences during ERASE SUSPEND can introduce ambi-
guity into status register results.
Following protection configuration setup (60h), an
invalid command produces a lock command error (SR4
and SR5 are set to “1”) in the status register. If a lock
command error occurs during an ERASE SUSPEND,
SR4 and SR5 are set to “1” and remain at “1” after the
ERASE SUSPEND command is issued. When the ERASE
is complete, any possible error during the ERASE can-
not be detected via the status register because of the
previous locking command error.
A similar situation happens if an error occurs during
a program operation error nested within an ERASE
SUSPEND.
CHIP PROTECTION REGISTER
A 128-bit chip protection register can be used to
fullfill the security considerations in the system (pre-
venting device substitution).
The 128-bit security area is divided into two 64-bit
segments. The first 64 bits are programmed at the
manufacturing site with a unique 64-bit number. The
other segment is left blank for customers to program as
desired. (See Figure 9).
READING THE CHIP PROTECTION REGISTER
The chip protection register is read in the device
identification mode, loading the 90h command. Once
in this mode, READ cycles from addresses shown in
Table 9 retrieve the specified information. To return to
the read array mode, write the READ ARRAY command
(FFh).
PAGE READ MODE
The initial portion of the page mode cycle is the
same as the asynchronous access cycle. Holding CE#
LOW and toggling addresses A0–A1 allows random ac-
cess of other words in the page.
The page size can be customized at the factory to
four or eight words as required; but if no specification is
made, the normal size is four words.
ASYNCHRONOUS READ CYCLE
When accessing addresses in a random order or
when switching between pages, the access time is given
by
t
AA.
When F_CE# and F_OE# are LOW, the data is placed
on the data bus and the processor can read the data.
Figure 9
Protection Register Memory Map
4 Words
Factory-Programmed
4 Words
User-Programmed
PR Lock
0
88h
85h
84h
81h
80h
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