
S
36
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
 256K x 16 SRAM COMBO MEMORY
ADVANCE
SRAM OPERATING MODES
SRAM READ ARRAY
The operational state of the SRAM is determined by
S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as
indicated in the Truth Table. To perform an SRAM
READ operation, S_CE1#, and S_OE#, must be at V
IL
,
and S_CE2 and S_WE# must be at V
IH
. When in this
state, S_UB# and S_LB# control whether the lower byte
is read (S_UB# V
IH
, S_LB# V
IL
), the upper byte is read
(S_UB# V
IL
, S_LB# V
IH
), both upper and lower bytes are
read (S_UB# V
IL
, S_LB# V
IL
), or neither are read (S_UB#
V
IH
, S_LB# V
IH
) and the device is in a standby state.
While performing an SRAM READ operation, cur-
rent consumption may be reduced by reading within a
16-word page. This is done by holding S_CE1# and
SRAM FUNCTIONAL BLOCK DIAGRAM
DQ0–DQ7
WORD
ADDRESS
DECODE
LOGIC
PAGE
ADDRESS
DECODE
LOGIC
CONTROL
LOGIC
16K-PAGE
x16 WORD
x16 BIT
RAM ARRAY
WORD
MUX
DQ8–DQ15
INPUT/
OUTPUT
MUX
AND
BUFFERS
S_CE1#
S_CE2
S_WE#
A4–A17
A0–A3
S_OE#
S_UB#
S_LB#
S_OE# at V
IL
, S_WE# and S_CE2 at V
IH
, and toggling
addresses A0–A3. S_UB# and S_LB# control the data
width as described above.
SRAM WRITE ARRAY
In order to perform an SRAM WRITE operation,
S_CE1# and S_WE# must be at V
IL
, and S_CE2 and
S_OE# must be at V
IH
. When in this state, S_UB# and
S_LB# control whether the lower byte is written (S_UB#
V
IH
, S_LB# V
IL
), the upper byte is written (S_UB# V
IL
,
S_LB# V
IH
), both upper and lower bytes are written
(S_UB# V
IL
, S_LB# V
IL
), or neither are written (S_UB#
V
IH
, S_LB# V
IH
) and the device is in a standby state.