參數(shù)資料
型號(hào)： MT28C3224P20
廠商： Micron Technology, Inc.
元件分類(lèi)： DRAM
英文描述： FLASH AND SRAM COMBO MEMORY
中文描述： 閃存和SRAM式內(nèi)存
文件頁(yè)數(shù)： 37/42頁(yè)
文件大小： 498K
代理商： MT28C3224P20
S
37
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
TIMING TEST CONDITIONS
Input pulse levels....................0.1V V
CC
to 0.9V V
CC
Input rise and fall times .................................... 5ns
Input timing reference levels ......................... 0.5V
Output timing reference levels ..................... 0.5V
Operating Temperature ............... -40
o
C to +85
o
C
SRAM WRITE CYCLE TIMING
-80/-85
DESCRIPTION
Write cycle time
Chip enable to end of write
Address valid to end of write
Byte select to end of write
Address setup time
Write pulse width
Write recovery time
Write to High-Z output
Data to write time overlap
Data hold from write time
End write to Low-Z output
SYMBOL
t
WC
t
CW
t
AW
t
LBW,
t
UBW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
MIN
MAX
85
50
50
50
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
50
0
0
50
0
0
15
NOTE:
For input/output contacts, refer to the Capacitance Table.
SRAM READ CYCLE TIMING
-80/-85
V
CC
= 1.70V–1.90V
MIN
V
CC
= 1.80V–2.20V
MIN
DESCRIPTION
Read cycle time
Address access time
Chip enable to valid output
Output enable to valid output
Byte select to valid output
Chip enable to Low-Z output
Output enable to Low-Z output
Byte select to Low-Z output
Chip enable to High-Z output
Output disable to High-Z output
Byte select disable to High-Z output
Output hold from address change
SYMBOL
t
RC
t
AA
t
CO
t
OE
t
LB,
t
UB
t
LZ
t
OLZ
t
LBZ,
t
UBZ
t
HZ
t
OHZ
t
LBHZ,
t
UBHZ
t
OH
MAX
100
100
100
35
100
MAX
85
85
85
35
85
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
0
0
0
0
0
5
0
0
0
0
0
0
5
15
15
15
15
15
15
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