參數(shù)資料
型號(hào)： MT28C3224P20
廠商： Micron Technology, Inc.
元件分類： DRAM
英文描述： FLASH AND SRAM COMBO MEMORY
中文描述： 閃存和SRAM式內(nèi)存
文件頁(yè)數(shù)： 19/42頁(yè)
文件大?。?/td> 498K
代理商： MT28C3224P20
F
19
2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory
MT28C3224P20_3.p65 – Rev. 3, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
256K x 16 SRAM COMBO MEMORY
ADVANCE
YES
NO
Full Status Register
Check (optional)
NO
YES
ERASE
SUSPEND
SR 7 = 1
Start
BLOCK ERASE Passed
V
PP
Range Error
BLOCK ERASE Failed
FULL STATUS REGISTER CHECK FLOW
Read Status Register
Bits
ERASE
SUSPEND Loop
1
YES
NO
SR1 = 0
YES
NO
YES
NO
BLOCK ERASE
Completed
Read Status Register
Bits
ERASE Attempted
on a Locked Block
SR3 = 0
SR5 = 0
Issue ERASE SETUP
Command and
Block Address
Issue BLOCK ERASE
CONFIRM Command
and Block Address
Figure 6
BLOCK ERASE Flowchart
NOTE:
1. Full status register check can be done after each block or after a sequence of blocks.
2. SR3 must be cleared before attempting additional PROGRAM/ERASE operations.
3. SR5 is cleared only by the CLEAR STATUS REGISTER command in cases where multiple blocks are erased before full
status is checked.
BUS
OPERATION COMMAND COMMENTS
WRITE
WRITE
ERASE
SETUP
WRITE
ERASE
Data =20h
Block Addr = Address
within block to be erased
Data =D0h
Block Addr = Address
within block to be erased
Status register data;
toggle OE# or CE# to
update status register.
Check SR7
1 = Ready, 0 = Busy
READ
Standby
Repeat for subsequent blocks.
Write FFh after the last BLOCK ERASE operation to
reset the device to read array mode.
BUS
OPERATION COMMAND COMMENTS
Standby
Check SR1
1 = Detect locked block
Check SR3
2
1 = Detect V
PP
block
Check SR4 and SR5
1 = BLOCK ERASE
command error
Check SR5
3
1 = BLOCK ERASE error
Standby
Standby
Standby
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