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參數(shù)資料
| 型號： | MT16LSDT464A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 64 SDRAM DIMMs(4M x 64同步動態(tài)RAM,雙列直插存儲器模塊) |
| 中文描述： | 4梅格× 64 SDRAM的內(nèi)存插槽（4米× 64同步動態(tài)內(nèi)存，雙列直插存儲器模塊） |
| 文件頁數(shù)： | 8/19頁 |
| 文件大?。?/td> | 257K |
| 代理商： | MT16LSDT464A |
2, 4 Meg x 64 SDRAM DIMMs
ZM02.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
8
2, 4 MEG x 64
SDRAM DIMMs
OBSOLETE
NOTE:
1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.”
SERIAL PRESENCE-DETECT MATRIX
BYTE
0
1
2
3
4
5
DESCRIPTION
ENTRY (VERSION)
128
256
SDRAM
11
9
1 (16MB)
2 (32MB)
64
0
LVTTL
8 (-10B)
10 (-662)
6 (-10B)
7.5 (-662)
NONPARITY
15.6
μ
s/SELF
8
NONE
1
SYMBOL BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
t
CK
1
0
0
1
0
1
t
AC
0
1
1
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
t
CCD
0
0
0
HEX
80
08
04
0B
09
01
02
40
00
01
80
A0
60
75
00
80
08
00
01
NUMBER OF BYTES USED BY MICRON
TOTAL NUMBER OF SPD MEMORY BYTES
MEMORY TYPE
NUMBER OF ROW ADDRESSES
NUMBER OF COLUMN ADDRESSES
NUMBER OF BANKS
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
0
0
0
1
6
7
8
9
MODULE DATA WIDTH
MODULE DATA WIDTH (continued)
MODULE VOLTAGE INTERFACE LEVELS
SDRAM CYCLE TIME
(CAS LATENCY = 3)
SDRAM ACCESS FROM CLOCK
(CAS LATENCY = 3)
MODULE CONFIGURATION TYPE
REFRESH RATE/TYPE
SDRAM WIDTH (PRIMARY SDRAM)
ERROR-CHECKING SDRAM DATA WIDTH
MINIMUM CLOCK DELAY FROM BACK-TO-BACK
RANDOM COLUMN ADDRESSES
BURST LENGTHS SUPPORTED
NUMBER OF BANKS ON SDRAM DEVICE
CAS LATENCIES SUPPORTED
CS LATENCY
WE LATENCY
SDRAM MODULE ATTRIBUTES
SDRAM DEVICE ATTRIBUTES: GENERAL
SDRAM CYCLE TIME
(CAS LATENCY = 2)
SDRAM ACCESS FROM CLK
(CAS LATENCY = 2)
SDRAM CYCLE TIME
(CAS LATENCY = 1)
SDRAM ACCESS FROM CLK
(CAS LATENCY = 1)
MINIMUM ROW PRECHARGE TIME
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1, 2, 4, 8 PAGE
2
1, 2, 3
0
0
NONBUFFERED
0E
12 (-10B)
15 (-662)
9
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
1
1
1
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
0
0
8F
02
07
01
01
00
0E
C0
F0
90
t
CK
24
t
AC
25
30
t
CK
0
1
1
1
1
0
0
0
78
26
27
t
AC
0
1
1
0
1
1
0
0
6C
27
24 (-10B)
30 (-662)
20
20 (-10B)
30 (-662)
50 (-10B)
60 (-662)
16MB
2 (-10B)
0 (-662)
t
RP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
0
0
0
1
1
1
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
18
1E
14
14
1E
32
3C
04
20
00
28
29
MINIMUM ROW ACTIVE TO ROW ACTIVE
MINIMUM RAS# TO CAS# DELAY
t
RRD
t
RCD
30
MINIMUM RAS# PULSE WIDTH
t
RAS
31
32
MODULE BANK DENSITY
COMMAND AND ADDRESS SETUP TIME
t
AS,
t
CMS
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