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| 型號(hào)： | MT16LSDT464A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 64 SDRAM DIMMs(4M x 64同步動(dòng)態(tài)RAM,雙列直插存儲(chǔ)器模塊) |
| 中文描述： | 4梅格× 64 SDRAM的內(nèi)存插槽（4米× 64同步動(dòng)態(tài)內(nèi)存，雙列直插存儲(chǔ)器模塊） |
| 文件頁(yè)數(shù)： | 11/19頁(yè) |
| 文件大?。?/td> | 257K |
| 代理商： | MT16LSDT464A |
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2, 4 Meg x 64 SDRAM DIMMs
ZM02.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
11
2, 4 MEG x 64
SDRAM DIMMs
OBSOLETE
NOTE:
1. For a burst length of two, A1-A8 select the block-of-
two burst; A0 selects the starting column within the
block.
2. For a burst length of four, A2-A8 select the block-of-
four burst; A0-A1 select the starting column within
the block.
3. For a burst length of eight, A3-A8 select the block-of-
eight burst; A0-A2 select the starting column within
the block.
4. For a full-page burst, the full row is selected, and
A0-A8 select the starting column.
5. Whenever a boundary of the block is reached within
a given sequence above, the following access wraps
within the block.
6. For a burst length of one, A0-A8 select the unique
column to be accessed, and Mode Register bit M3 is
ignored.
Table 1
BURST DEFINITION
Burst
Length
Starting Column
Address
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
2
0-1
1-0
0-1
1-0
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
4
A2
0
0
0
0
1
1
1
1
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
8
Full
Page
(512)
n = A0-A8
Not Supported
(location 0-511)
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
1
2
3
Reserved
Reserved
Reserved
Reserved
M6
0
0
0
0
1
1
1
1
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
Burst Length
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M3
M6-M0
M8
M7
Op Mode
A10
BA
10
11
Reserved*
WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
Figure 1
MODE REGISTER DEFINITION
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