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參數(shù)資料
| 型號(hào)： | MT16LSDT464A |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 4 Meg x 64 SDRAM DIMMs(4M x 64同步動(dòng)態(tài)RAM,雙列直插存儲(chǔ)器模塊) |
| 中文描述： | 4梅格× 64 SDRAM的內(nèi)存插槽（4米× 64同步動(dòng)態(tài)內(nèi)存，雙列直插存儲(chǔ)器模塊） |
| 文件頁(yè)數(shù)： | 6/19頁(yè) |
| 文件大?。?/td> | 257K |
| 代理商： | MT16LSDT464A |
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2, 4 Meg x 64 SDRAM DIMMs
ZM02.p65 – Rev. 6/98
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1998, Micron Technology, Inc.
6
2, 4 MEG x 64
SDRAM DIMMs
OBSOLETE
PIN DESCRIPTIONS
PIN NUMBERS
115, 111, 27
SYMBOL
RAS#, CAS#,
WE#
CK0-CK3
TYPE
Input
DESCRIPTION
Command Inputs: RAS#, CAS# and WE# (along with
S0#-S3#) define the command being entered.
Clock: CK0-CK3 are driven by the system clock. All
SDRAM input signals are sampled on the positive edge of
CK. CK also increments the internal burst counter and
controls the output registers.
Clock Enable: CKE0-CKE1 activate (HIGH) and deactivate
(LOW) the CK0-CK3 signals. Deactivating the clock
provides POWER-DOWN and SELF REFRESH operation
(all banks idle) or CLOCK SUSPEND operation (burst
access in progress). CKE0-CKE1 are synchronous except
after the device enters power-down and self refresh modes,
where CKE0-CKE1 become asynchronous until after
exiting the same mode. The input buffers, including CK0-
CK3, are disabled during power-down and self refresh
modes, providing low standby power.
Chip Select: S0#-S3# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands
are masked when S0#-S3# are registered HIGH. S0#-S3#
are considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for
write accesses and an output enable signal for read
accesses. Input data is masked when DQMB is sampled
HIGH during a WRITE cycle. The output buffers are placed
in a High-Z state (two-clock latency) when DQMB is
sampled HIGH during a READ cycle.
Bank Address: BA0 defines to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being
applied. BA0 is also used to program the 12th bit of the
Mode Register.
Address Inputs: A0-A10 are sampled during the ACTIVE
command (row-address A0-A10) and READ/WRITE
command (column-address A0-A8, with A10 defining
AUTO PRECHARGE) to select one location out of the
memory array in the respective bank. A10 is sampled
during a PRECHARGE command to determine if both
banks are to be precharged (A10 HIGH). The address
inputs also provide the op-code during a LOAD MODE
REGISTER command.
Data I/O: Data bus.
42, 125, 79, 163
Input
128, 63
CKE0, CKE1
Input
30, 114, 45, 129
S0#-S3#
Input
28-29, 46-47,
112-113, 130-131
DQMB0-DQMB7
Input
122
BA0
Input
33-38, 117-121
A0-A10
Input
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89, 91-95,
97-101, 103, 104,
139-142, 144, 149-151,
153-156, 158-161
DQ0-DQ63
Input/
Output
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| MT16LSDT6464A | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM MODULE |
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| MT16LSDT6464AG-10EC2 | 制造商:Micron Technology Inc 功能描述:DRAM MOD SDRAM 4GBIT 168UDIMM - Trays |
| MT16LSDT6464AG-133 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:SYNCHRONOUS DRAM MODULE |
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