參數(shù)資料
型號(hào)： MSC8144EC
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類： 數(shù)字信號(hào)處理
英文描述： Quad Core Digital Signal Processor
中文描述： 四核心數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 76/80頁(yè)
文件大?。?/td> 1145K
代理商： MSC8144EC
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Product Documentation
Freescale Semiconductor
76
6
Product Documentation
MSC8144EC Technical Data Sheet
(MSC8144EC). Details the signals, AC/DC characteristics, clock signal
characteristics, package and pinout, and electrical design considerations of the MSC8144EC device.
MSC8144EC Reference Manual
(MSC8144ECRM). Includes functional descriptions of the extended cores and all the
internal subsystems including configuration and programming information.
Application Notes
. Cover various programming topics related to the StarCore DSP core and the MSC8144EC device.
SC3400 DSP Core Reference Manual
. Covers the SC3400 core architecture, control registers, clock registers, program
control, and instruction set.
MSC8144 SC3400 DSP Core Subsystem Reference Manual
. Covers core subsystem architecture, functionality, and
registers.
7
Revision History
Table 72
provides a revision history for this data sheet.
Table 71. Document Revision History
Revision
Date
Description
0
1
June 2007
Sep 2007
Initial public release.
Updated M3 voltage range in
Table 3
.
Changed note in
Table 7
for PLL power supplies.
DDR voltage designator changed from V
DD
to V
DDDDR
in
Table 8
,
Table 10
,
Section 2.7.4.1
,
Section
2.7.4.2
, and
Figure 11
. Changed range on I
OZ
in
Table 8
and
Table 10
.
Deleted text before
Table 13
and added note 2 to input pin capacitance.
Deleted text before
Table 14
, added a 1 to the note, and added note 1 to input pin capacitance.
Deleted
Section 2.6.5
on page 32 and renumbered subsequent subsections.
Deleted text before new
Section 2.6.5.1
.
Added a 1 to the note in
Table 15
and added note 1 to input pin capacitance.
Deleted ac voltage rows from
Table 16
. Added note 1 to input pin capacitance.
Changed output high and low voltage levels in
Table 17
and
Table 18
.
Deleted text before
Table 19
.
Added clock skew ranges in percent in
Table 21
.
Changed V
REF
to MV
REF
in
Table 26
.
Changed V
DD
to V
DDIO
in
Table 41
Updated note 2.
Added note 4 to
Table 42
. Changed t
TDMSHOX
value.
Changed V
DD
to V
DDGE
in
Figure 27
and
Figure 30
.
Changed the value of the data to clock out skew in
Table 51
.
Changed EE pin timing in
Table 55
.
Changed the head for the JTAG timing section, now
Section 2.7.15
.
Updated JTAG timing for TCK cycle time, TCK high phase, and boundary scan input data hold time in
Table 56
.
Added new
Section 3.4
with guidelines for board layout for clock and timing signals. Renumbered
subsequent sections.
Changed leakage current values in
Table 13
,
Table 14
,
Table 15
,
Table 16
,
Table 17
,
Table 18
, and
Table 19
from –10 and 10
μ
a to –30 and 30
μ
a.
Change the minimum value of t
MDDVKH
in
Table 45
from 5 ns to 7 ns.
Updated note 1 in
Table 45
.
Corrected column numbering in
Figure 3
and
Figure 4
.
Updated SPI signal names in
Table 1
.
Updated SPI signal names in
Table 1
.
2
Sep 2007
3
Oct 2007
4
Oct 2007
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MSC8144ESVT800B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 800MHZ 800MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
MSC8144ETVT1000A 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA - Bulk
MSC8144ETVT1000B 制造商:Freescale Semiconductor 功能描述:DSP 32-BIT 1GHZ 1000MIPS 783-PIN FCBGA EACH - Bulk 制造商:Freescale Semiconductor 功能描述:ENCRYPTION PACSUN R2.1 783FCPBGA
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