參數(shù)資料
型號： MSC8144EC
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： Quad Core Digital Signal Processor
中文描述： 四核心數(shù)字信號處理器
文件頁數(shù)： 30/80頁
文件大?。?/td> 1145K
代理商： MSC8144EC
MSC8144EC Quad Core Digital Signal Processor Data Sheet, Rev. 6
Electrical Characteristics
Freescale Semiconductor
30
Table 9
provides the DDR capacitance when
V
DDDDR
(typ) = 1.8 V.
2.6.1.2
DDR (2.5V) SDRAM DC Electrical Characteristics
Table 10
provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144EC when
V
DDDDR
(typ) = 2.5 V.
Table 11
provides the DDR capacitance when
V
DDDDR
(typ) = 2.5 V.
Table 12
lists the current draw characteristics for
MV
REF
.
Table 9. DDR2 SDRAM Capacitance for V
DDDDR
(typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
Input/output capacitance: DQ, DQS, DQS
C
IO
6
8
pF
Delta input/output capacitance: DQ, DQS, DQS
C
DIO
—
0.5
pF
Note:
This parameter is sampled. V
DDDDR
= 1.8 V
±
0.090 V, f = 1 MHz, T
A
= 25°C, V
OUT
= V
DDDDR
/2, V
OUT
(peak-to-peak) = 0.2 V.
Table 10. DDR SDRAM DC Electrical Characteristics for V
DDDDR
(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
I/O supply voltage
1
V
DDDDR
2.3
2.7
V
I/O reference voltage
2
MV
REF
0.49
×
V
DDDDR
0.51
×
V
DDDDR
V
I/O termination voltage
3
V
TT
MV
REF
– 0.04
MV
REF
+ 0.04
V
Input high voltage
V
IH
MV
REF
+ 0.15
V
DDDDR
+ 0.3
V
Input low voltage
V
IL
–0.3
MV
REF
– 0.15
V
Output leakage current
4
I
OZ
–50
50
μ
A
Output high current (V
OUT
= 1.95 V)
I
OH
–16.2
—
mA
Output low current (V
OUT
= 0.35 V)
I
OL
16.2
—
mA
Notes:
1.
2.
V
DDDDR
is expected to be within 50 mV of the DRAM V
DD
at all times.
MV
REF
is expected to be equal to 0.5
×
V
DDDDR
, and to track V
DDDDR
DC variations as measured at the receiver.
Peak-to-peak noise on MV
REF
may not exceed
±
2% of the DC value.
V
TT
is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MV
REF
. This rail should track variations in the DC level of V
DDDDR
.
Output leakage is measured with all outputs are disabled, 0 V
≤
V
OUT
V
DDDDR
.
3.
4.
Table 11. DDR SDRAM Capacitance for V
DDDDR
(typ) = 2.5 V
Parameter/Condition
Symbol
Min
Max
Unit
Input/output capacitance: DQ, DQS
C
IO
6
8
pF
Delta input/output capacitance: DQ, DQS
C
DIO
—
0.5
pF
Note:
This parameter is sampled. V
DDDDR
= 2.5 V
±
0.125 V, f = 1 MHz, T
A
= 25°C, V
OUT
= V
DDDDR
/2, V
OUT
(peak-to-peak) = 0.2 V.
Table 12. Current Draw Characteristics for MV
REF
Parameter / Condition
Symbol
Min
Max
Unit
Current draw for MV
REF
I
MVREF
—
500
μ
A
Note:
The voltage regulator for MV
REF
must be able to supply up to 500
μ
A current.
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